DSPIC30F6012AT-20I/PT Microchip Technology, DSPIC30F6012AT-20I/PT Datasheet - Page 139

• Manufacturer Part Number: DSPIC30F6012AT-20I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012AT-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following figure depicts the recommended circuit
for the conversion rates above 100 ksps. The
dsPIC30F6014A is shown as an example.
FIGURE 19-2:
The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
19.7.1
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 19-2.
• Connect external V
• Set SSRC<2.0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Write the SMPI<3.0> control bits in the ADCON2
© 2005 Microchip Technology Inc.
the recommended circuit shown in Figure 19-2.
enable the auto convert option.
control bit in the ADCON1 register.
register for the desired number of conversions
between interrupts.
C2
0.1 F
R2
10
V
DD
V
DD
200 KSPS CONFIGURATION
GUIDELINE
C1
0.01 F
REF
dsPIC30F6011A/6012A/6013A/6014A
ADC VOLTAGE REFERENCE SCHEMATIC
1
2
3
4
5
6
7
8
9
10
V
V
13
14
15
16
17
18
19
20
+ and V
SS
DD
R1
10
REF
- pins following
V
DD
dsPIC30F6014A
V
Preliminary
DD
Note 1: Ensure adequate bypass capacitors are provided on each V
V
DD
• Configure the ADC clock period to be:
• Configure the sampling time to be 1 T
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 19-1 for code
example.
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
writing: SAMC<4:0> = 00001.
(14 + 1) x 200,000
V
V
60
59
58
57
56
55
54
53
52
50
49
DD
47
46
45
44
43
42
41
SS
1
V
See Note 1:
DD
C8
1 F
C5
1 F
V
AV
= 334 ns
DD
AD
DD
C7
0.1 F
C4
0.1 F
selection in conjunc-
DS70143B-page 137
V
AV
DD
AD
DD
C6
0.01 F
C3
0.01 F
by
DD
V
AV
DD
pin.
DD