AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 124
AT89C51SND1C-7HTUL
Manufacturer Part Number
AT89C51SND1C-7HTUL
Description
IC MCU 64KB FLASH MEM 81-CBGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT80C51SND1C-ROTIL.pdf
(213 pages)
Specifications of AT89C51SND1C-7HTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
81-CBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 16-21. MMC Controller Interrupt System
16.8
124
Registers
AT8xC51SND1C
MMINT.7
MMINT.6
MMINT.5
MMINT.4
MMINT.3
MMINT.2
MMINT.1
MMINT.0
MCBI
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
The interrupt request is generated each time an unmasked flag is set, and the global MMC con-
troller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This
implies that register content must be saved and tested interrupt flag by interrupt flag to be sure
not to forget any interrupts.
Table 113. MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
Number
DRPTR
MMMSK.6
MMMSK.4
MMMSK.2
MMMSK.0
EORM
EOFM
Bit
F1FM
F1EM
7
7
Mnemonic Description
MMMSK.7
MMMSK.5
MMMSK.3
MMMSK.1
DRPTR
DTPTR
MCBM
EOCM
F2FM
F2EM
Bit
6
Data Receive Pointer Reset Bit
Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
CRPTR
5
CTPTR
4
EMMC
IEN1.0
MBLOCK
3
MMC Interface
Interrupt Request
DFMT
2
RFMT
1
4109L–8051–02/08
CRCDIS
0
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