AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 13
AT89C51SND1C-7HTUL
Manufacturer Part Number
AT89C51SND1C-7HTUL
Description
IC MCU 64KB FLASH MEM 81-CBGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT80C51SND1C-ROTIL.pdf
(213 pages)
Specifications of AT89C51SND1C-7HTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
81-CBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5. Clock Controller
5.1
5.2
4109L–8051–02/08
Oscillator
X2 Feature
The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an on-chip Phase
Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this
controller.
The AT8xC51SND1C X1 and X2 pins are the input and the output of a single-stage on-chip
inverter (see Figure 5-1) that can be configured with off-chip components such as a Pierce oscil-
lator (see Figure 5-2). Value of capacitors and crystal characteristics are detailed in the
Section “DC Characteristics”, page 163.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a
clock for the peripherals as shown in Figure 5-1. These clocks are either enabled or disabled,
depending on the power reduction mode as detailed in the section
page
Port sampling clocks.
Figure 5-1.
Figure 5-2.
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the
AT8xC51SND1C need only 6 oscillator clock periods per machine cycle. This feature called the
“X2 feature” can be enabled using the X2 bit
AT8xC51SND1C to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in
Figure 5-1, both CPU and peripheral clocks are affected by this feature. Figure 5-3 shows the X2
mode switching waveforms. After reset the standard mode is activated. In standard mode the
CPU and peripheral clock frequency is the oscillator frequency divided by 2 while in X2 mode, it
48. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, ADC, SPI, and
X1
X2
Oscillator Block Diagram and Symbol
Crystal Connection
Peripheral Clock Symbol
CLOCK
PCON.1
PER
PD
VSS
CPU Core Clock Symbol
C1
C2
÷
(1)
2
CLOCK
CPU
in CKCON (see Table 16) and allows the
CKCON.0
Q
X2
0
1
X1
X2
AT8xC51SND1C
PCON.0
IDL
“Power Management” on
Oscillator Clock Symbol
CLOCK
OSC
Peripheral
Clock
CPU Core
Clock
Oscillator
Clock
13
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