AT91SAM9261SB-CU Atmel, AT91SAM9261SB-CU Datasheet
AT91SAM9261SB-CU
Specifications of AT91SAM9261SB-CU
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AT91SAM9261SB-CU Summary of contents
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Features • Incorporates the ARM926EJ-S™ ARM – DSP Instruction Extensions ® – ARM Jazelle Technology for Java – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit ™ – ...
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... Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel EEPROMs Supported ® • IEEE 1149.1 JTAG Boundary Scan on All Digital Pins • ...
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Description The AT91SAM9261S is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261S is an optimized host processor for ...
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Block Diagram Figure 2-1. AT91SAM9261S Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG ...
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Signal Description Table 3-1. Signal Description by Peripheral Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDPLL PLL Power Supply VDDOSC Oscillator Power Supply VDDCORE Core ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - PA31 Parallel IO Controller A PB0 - PB31 Parallel IO Controller B PC0 - PC31 Parallel IO Controller ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function SCK0 - SCK2 Serial Clock TXD0 - TXD2 Transmit Data RXD0 - RXD2 Receive Data RTS0 - RTS2 Request To Send CTS0 - CTS2 Clear To Send TD0 - TD2 ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function HDMA USB Host Port A Data - HDPA USB Host Port A Data + HDMB USB Host Port B Data - HDPB USB Host Port B Data + AT91SAM9261S 8 ...
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Package and Pinout The AT91SAM9261S is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9261S Mechanical ...
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Pinout Table 4-1. AT91SAM9261S Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC ...
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Power Considerations 5.1 Power Supplies The AT91SAM9261S has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: ...
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Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma- nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this ...
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Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
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Debug and Test Features • Integrated Embedded In-circuit Emulator Real-Time – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • ...
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Memories Figure 8-1. AT91SAM9261S Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF ...
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space ...
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Internal Memory Mapping Table 8-3 status and the BMS state at reset. Table 8-3. Internal Memory Mapping Address Master 0: ARM926 Instruction REMAP(RCB0 BMS = 1 0x0000 0000 Int. ROM Note: 1. EBI NCS0 ...
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BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. • Enable the 32,768 Hz oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Automatic ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF ...
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Block Diagram Figure 9-1. System Controller Block Diagram periph_irq[2..21] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset VDDCORE Powered NRST VDDCORE POR VDDBU POR backup_nreset SHDN WKUP backup_nreset VDDBU Powered XIN32 SLOW CLOCK XOUT32 OSC XIN MAIN ...
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Reset Controller • Based on two Power-on-Reset cells • Status of the last reset – Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset • Controls the internal resets and the NRST pin output 9.3 ...
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Power Management Controller • The Power Management Controller provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clock USBCK (HCK0) – the LCD Controller Clock LCDCK (HCK1) – thirty peripheral clocks – ...
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... Chip ID Registers – ICE Access Prevention • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...
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Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of • ICE Access prevention – Enables software to prevent system access ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory ...
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Peripheral Multiplexing on PIO Lines The AT91SAM9261S features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one ...
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SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard useful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI. 10.3.1.7 USARTs • Using USART0 with its ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A Peripheral B PA0 SPI0_MISO MCDA0 PA1 SPI0_MOSI MCCDA PA2 SPI0_SPCK MCCK PA3 SPI0_NPCS0 PA4 SPI0_NPCS1 MCDA1 PA5 SPI0_NPCS2 MCDA2 PA6 SPI0_NPCS3 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 LCDVSYNC PB1 LCDHSYNC PB2 LCDDOTCK PCK0 (1) PB3 LCDDEN PB4 LCDCC LCDD2 PB5 LCDD0 LCDD3 PB6 LCDD1 LCDD4 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Peripheral B PC0 NANDOE NCS6 PC1 NANDWE NCS7 PC2 NWAIT IRQ0 PC3 A25/CFRNW PC4 NCS4/CFCS0 PC5 NCS5/CFCS1 PC6 CFCE1 PC7 CFCE2 ...
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System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • ...
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Static Memory Controller • External memory mapping, 256 Mbyte address space per Chip Select Line • Eight Chip Select Lines • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte ...
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Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, ...
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Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, ...
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USB • USB Host Port: – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with ...
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Package Drawing Figure 11-1. 217-ball LFBGA Package Drawing AT91SAM9261S 36 6242ES–ATARM–11-Sep-09 ...
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... AT91SAM9261S Ordering Information Table 12-1. AT91SAM9261S Ordering Information Ordering Code AT91SAM9261S-CJ AT91SAM9261SB-CU 6242ES–ATARM–11-Sep-09 Package Package Type BGA217 RoHS-compliant BGA217 RoHS-compliant AT91SAM9261S Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C 37 ...
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... Section 8.1.2.1 “BMS = 1, Boot on Embedded ROM” “Features” 6242DS Additional Embedded Memories, 16 Kbytes SRAM updated. Debug Unit (DBGU) updated. Section 12. “AT91SAM9261S Ordering Information” 6242CS Updated with Revision B Parts: AT91SAM9261SB-CU Section 7.2 “Debug and Test 6242BS Section 12. “AT91SAM9261S Ordering Information” 6242AS First Issue AT91SAM9261S 38 updated ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...