ATMEGA164P-15AZ Atmel, ATMEGA164P-15AZ Datasheet
ATMEGA164P-15AZ
Specifications of ATMEGA164P-15AZ
Available stocks
Related parts for ATMEGA164P-15AZ
ATMEGA164P-15AZ Summary of contents
Page 1
... TQFP, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega164P/324P/644P • Speed Grades – ATmega164P/324P/644P 8MHz @ 2.7 - 5.5V 16MHz @ 4.5 - 5.5V • Power Consumption at 8 MHz, 5V, 25°C for ATmega644P – Active mode – Idle mode: 2.4 mA – Power-down Mode: 0.8 µA ® ...
Page 2
... Figure 1-1. (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT/RXD1/26/INT0) PD2 Note: ATmega164P/324P/644P 2 Pinout ATmega164P/324P/644P (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. TQFP/QFN/MLF ...
Page 3
... Overview The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
Page 4
... Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel- opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
Page 5
... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega164P/324P/644P as listed on 7674F–AVR–09/09 ...
Page 6
... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega164P/324P/644P as listed on 2.3.7 RESET Reset input ...
Page 7
... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 7674F–AVR–09/09 ATmega164P/324P/644P 7 ...
Page 8
... The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc- tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". ATmega164P/324P/644P 8 7674F–AVR–09/09 ...
Page 9
... The program memory is In-System Reprogrammable Flash memory. 7674F–AVR–09/09 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega164P/324P/644P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 10
... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega164P/324P/644P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 11
... The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag 7674F–AVR–09/09 ATmega164P/324P/644P ...
Page 12
... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATmega164P/324P/644P 12 shows the structure of the 32 general purpose working registers in the CPU. ...
Page 13
... Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 7674F–AVR–09/09 The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATmega164P/324P/644P Figure 5- R26 (0x1A R28 (0x1C R30 (0x1E ...
Page 14
... Figure 5-4. 1st Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 5-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. ATmega164P/324P/644P – – – ...
Page 15
... Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. “Memory Programming” on page ATmega164P/324P/644P T2 T3 “Memory Program- “Interrupts” on page 60. The list also “Interrupts” on page 60 for more information. 296. T4 ...
Page 16
... C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ ATmega164P/324P/644P 16 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ...
Page 17
... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. 7674F–AVR–09/09 ATmega164P/324P/644P 17 ...
Page 18
... AVR Memories 6.1 Overview This section describes the different memories in the ATmega164P/324P/644P. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164P/324P/644P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
Page 19
... SRAM Data Memory Figure 6-2 The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 20
... The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible through all these addressing modes. The Register File is described in ter File” on page Figure 6-2. 6.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access ...
Page 21
... EEPROM Data Memory The ATmega164P/324P/644P contains 512B/1K/2K bytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 22
... The I/O space definition of the ATmega164P/324P/644P is shown in page 356. All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 23
... Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bits 11:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space ...
Page 24
... EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. ATmega164P/324P/644P 24 EEPROM Mode Bits Programming ...
Page 25
... The calibrated Oscillator is used to time the EEPROM accesses. typical programming time for EEPROM access from the CPU. Table 6-2. Symbol EEPROM write (from CPU) 7674F–AVR–09/09 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega164P/324P/644P Table 6-2 on page 25 Typ Programming Time 3.3 ms lists the 25 ...
Page 26
... EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Note: ATmega164P/324P/644P Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ...
Page 27
... Read data from Data Register r16,EEDR in ret (1) /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 27 ...
Page 28
... GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 6.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 6.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value Note: ATmega164P/324P/644P MSB R/W R/W R MSB R/W R/W ...
Page 29
... Control Unit clk ASY Source clock System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator is halted, TWI address recognition in all sleep modes. I/O ATmega164P/324P/644P Flash and CPU Core RAM EEPROM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Watchdog clock ...
Page 30
... The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting using any available programming interface. ATmega164P/324P/644P 30 ASY Device Clocking Options Select 1. For all fuses “ ...
Page 31
... CC Table 7-2. The frequency of the Watchdog Oscillator is voltage Section 27. “ATmega644P Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 ATmega164P/324P/644P “On-chip Debug System” on page timed from the Watchdog TOUT = 3.0V) Number of Cycles 4.3 ms 512 (8,192) ...
Page 32
... The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3. Frequency Range Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 7-4. ATmega164P/324P/644P 32 Crystal Oscillator Connections C2 C1 33. Low Power Crystal Oscillator Operating Modes ...
Page 33
... The frequency ranges are preliminary values. Actual values are TBD MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device. ATmega164P/324P/644P Additional Delay from Reset ( ...
Page 34
... The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega164P/324P/644P oscillator is optimized for very low power consumption, and thus when selecting crystals, see 12.5 pF crystals Table 7-7 ...
Page 35
... Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Reserved 32K CK 32K CK 32K CK Reserved 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega164P/324P/644P TOSC2 TOSC1 Typ. (pF) Max. (pF) 8.0 Additional Delay from Reset (V = 5.0V) CKSEL0 CC (1) 14CK (1) 14CK + 4 ...
Page 36
... When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7-11 on page Table 7-11. Power Conditions BOD enabled Fast rising power Slowly rising power Note: ATmega164P/324P/644P 36 and Section 27.7 “Internal Oscillator Speed” on page 350 for more details. 331. “Calibration Byte” on page Internal Calibrated RC Oscillator Operating Modes ...
Page 37
... Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power-down and Power-save Reserved External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL Crystal Oscillator Clock Frequency Nominal Frequency kHz ATmega164P/324P/644P Table 7-12. CKSEL3..0 0011 Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms XTAL2 XTAL1 GND CKSEL3..0 0000 SUT1 ...
Page 38
... System Clock Prescaler The ATmega164P/324P/644P has a system clock prescaler, and the system clock can be divided by setting the to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 39
... CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value Table 26-2 on page 331. The application software can write this register to change 331. Calibration outside that range is not guaranteed. ATmega164P/324P/644P CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W OSCCAL ...
Page 40
... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-16. CLKPS3 ATmega164P/324P/644P CLKPCE – ...
Page 41
... SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 7674F–AVR–09/09 for more details. presents the different clock systems in the ATmega164P/324P/644P, and Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains X ...
Page 42
... ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7 pin change interrupt can wakeup the MCU from ADC Noise Reduction mode. ATmega164P/324P/644P 42 level has dropped during the sleep period ...
Page 43
... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 7674F–AVR–09/09 ATmega164P/324P/644P “External Interrupts” on page 66 “Clock Sources” on page 30. ...
Page 44
... If the reference is kept on in sleep mode, the output can be used immediately. Refer to age Reference” on page 53 ATmega164P/324P/644P 44 “PRR – Power Reduction Register” on page “AC - Analog Comparator” on page 240 for details on the start-up time. “ ...
Page 45
... input pin can cause significant current even in active mode. Digital CC “DIDR1 – Digital Input Disable Register 1” on page 242 for details. ATmega164P/324P/644P ) are stopped, the input buffers of the device will and “DIDR0 – Digital for details on 45 ...
Page 46
... The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. ATmega164P/324P/644P – ...
Page 47
... JTD BODS BODSE R/W R/W R 41. Writing to the BODS bit is controlled by a timed sequence and an enable bit PRTWI PRTIM2 PRTIM0 PRUSART1 R/W R/W R ATmega164P/324P/644P PUD – – IVSEL R R PRTIM1 PRSPI PRUSART0 R/W R/W R/W R/W ...
Page 48
... Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. ATmega164P/324P/644P 48 7674F–AVR–09/09 ...
Page 49
... Reset Sources The ATmega164P/324P/644P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 50
... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V ATmega164P/324P/644P 50 Reset Logic Power-on Reset Circuit ...
Page 51
... VCC Max. start voltage to ensure internal Power-on Reset signal VCC Min. start voltage to ensure internal Power-on Reset signal VCC Rise Rate to ensure Power-on Reset 1. Before rising, the supply has to be between “System and Reset Characteristics” on page ATmega164P/324P/644P CC V RST t TOUT Min Typ 1 ...
Page 52
... Figure 9-2. 9.0.5 Brown-out Detection ATmega164P/324P/644P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
Page 53
... Figure 9-4. 9.1 Internal Voltage Reference ATmega164P/324P/644P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.1.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
Page 54
... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 9.2.2 Overview ATmega164P/324P/644P has an Enhanced Watchdog Timer (WDT). The WDT is a timer count- ing cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...
Page 55
... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega164P/324P/644P 55 ...
Page 56
... WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATmega164P/324P/644P 56 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ...
Page 57
... To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 7674F–AVR–09/09 ATmega164P/324P/644P – ...
Page 58
... Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con- ditions causing failure, and a safe start-up after the failure. ATmega164P/324P/644P ...
Page 59
... WDP2 WDP1 WDP0 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles ATmega164P/324P/644P Typical Time-out at Cycles (2048) cycles 4K (4096) cycles 8K (8192) cycles 0.125 s Reserved = 5. 0.25 s 0.5 s 1.0 s 2.0 s 4 ...
Page 60
... Interrupts 10.1 Overview ATmega164P/324P/644P. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 10.2 Interrupt Vectors in ATmega164P/324P/644P Table 10-1. Vector No ATmega164P/324P/644P 60 15. Reset and Interrupt Vectors Program (2) Address Source (1) $0000 RESET $0002 INT0 $0004 INT1 $0006 ...
Page 61
... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 10-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega164P/324P/644P is: Address 0x0000 0x0002 0x0004 0x0006 ...
Page 62
... IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code 0x00000 RESET: ldi 0x00001 0x00002 0x00003 0x00004 0x00005 ; .org 0x1F002 0x1F002 0x1F004 ... 0x1FO36 ATmega164P/324P/644P 62 jmp TIM0_COMPB jmp TIM0_OVF jmp SPI_STC jmp USART0_RXC jmp USART0_UDRE jmp USART0_TXC jmp ...
Page 63
... RESET: ldi 0x1F03F 0x1F040 0x1F041 0x1F042 0x1FO43 10.2.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 7674F–AVR–09/09 ATmega164P/324P/644P Comments jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler ... ... ...
Page 64
... The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See the following Code Example. ATmega164P/324P/644P 64 7 ...
Page 65
... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); ATmega164P/324P/644P 65 ...
Page 66
... Initial Value • Bits 7:6 – Reserved These bits are reserved in the ATmega164P/324P/644P, and will always read as zero. • Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...
Page 67
... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed – – – – – – R for more information. ATmega164P/324P/644P – – INT2 INT1 R R R/W R – – INTF2 INTF1 R R ...
Page 68
... When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. ATmega164P/324P/644P ...
Page 69
... PCINT30 PCINT29 PCINT28 R/W R/W R/W R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R ATmega164P/324P/644P PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W ...
Page 70
... Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega164P/324P/644P ...
Page 71
... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 77. Refer to the individual module sections for a full description of the alter- ATmega164P/324P/644P Figure 12-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 90. “ ...
Page 72
... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. ATmega164P/324P/644P 72 (1) Pxn ...
Page 73
... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega164P/324P/644P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...
Page 74
... The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. ATmega164P/324P/644P 74 SYSTEM CLK X ...
Page 75
... Figure 12-2, the digital input signal can be clamped to ground at the input of the ATmega164P/324P/644P “Alternate Port Functions” on page / ...
Page 76
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. ATmega164P/324P/644P 76 or GND is not recommended, since this may cause excessive currents if the pin is CC ...
Page 77
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega164P/324P/644P Figure 12-2 on page 72 PUD ...
Page 78
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega164P/324P/644P 78 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...
Page 79
... ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4) ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3) ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2) ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1) ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0) ATmega164P/324P/644P . 79 ...
Page 80
... PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 12-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega164P/324P/644P 80 and Table 12-5 on page 80 Figure 12-5 on page Overriding Signals for Alternate Functions in PA7:PA4 PA7/ADC7/ PA6/ADC6/ PCINT7 PCINT6 PCINT7 • PCIE0 + PCINT6 • ...
Page 81
... AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PCINT10 (Pin Change Interrupt 10) T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9) T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8) ATmega164P/324P/644P Table 12-6. 81 ...
Page 82
... CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output during reset. PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source. ATmega164P/324P/644P 82 7674F–AVR–09/09 ...
Page 83
... OC0B 0 INT2 ENABLE PCINT11 • PCIE1 PCINT10 • PCIE1 1 1 INT2 INPUT PCINT11 INPUT PCINT10 INPUT – – ATmega164P/324P/644P PB5/MOSI/ PB4/SS/OC0B/ PCINT13 PCINT12 SPE • MSTR SPE • MSTR PORTB13 • PUD PORTB12 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • ...
Page 84
... TDO/PCINT20 – Port C, Bit 4 TDO, JTAG Test Data Output. PCINT20, Pin Change Interrupt source 20: The PC4 pin can serve as an external interrupt source. ATmega164P/324P/644P 84 Port C Pins Alternate Functions Alternate Function TOSC2 (Timer Oscillator pin 2) PCINT23 (Pin Change Interrupt 23) ...
Page 85
... AS2 • EXCLK AS2 0 0 AS2 • EXCLK AS2 AS2 • EXCLK + AS2 PCINT23 • PCIE2 0 EXCLK PCINT23 INPUT PCINT22 INPUT T/C2 OSC T/C2 OSC OUTPUT INPUT ATmega164P/324P/644P PC5/TDI/ PC4/TDO/ PCINT21 PCINT20 JTAGEN JTAGEN 1 1 JTAGEN JTAGEN SHIFT_IR + 0 SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 ...
Page 86
... DIEOE DIEOV DI AIO 12.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-12. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ATmega164P/324P/644P 86 PC3/TMS/ PC2/TCK/ PCINT19 PCINT18 JTAGEN JTAGEN 1 1 JTAGEN JTAGEN ...
Page 87
... TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. PCINT27, Pin Change Interrupt Source 27: The PD3 pin can serve as an external interrupt source. 7674F–AVR–09/09 ATmega164P/324P/644P 87 ...
Page 88
... PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt source. Table 12-13 on page 88 the overriding signals shown in Table 12-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega164P/324P/644P 88 and Table 12-14 on page 89 Figure 12-5 on page PD6/ICP1/ PD7/OC2A/ OC2B/ PCINT31 PCINT30 ...
Page 89
... When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega164P/324P/644P (1) PD1/TXD0/ ...
Page 90
... PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 12.3.10 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 12.3.11 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value ATmega164P/324P/644P JTD BODS BODSE PUD R R for more details about this feature ...
Page 91
... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega164P/324P/644P PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...
Page 92
... Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter- rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. ATmega164P/324P/644P 92 “Pin Configurations” on page “ ...
Page 93
... OCR0A Register. The assignment is depen- dent on the mode of operation. “Timer/Counter Prescaler” on page DATA BUS count clear TCNTn direction bottom ATmega164P/324P/644P for details. The Compare Match event will also 153. TOVn (Int.Req.) Clock Select Edge Detector clk ...
Page 94
... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 13-3 ATmega164P/324P/644P 94 Increment or decrement TCNT0 by 1. Select between increment and decrement. ...
Page 95
... This feature allows OCR0x to be initial- ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 7674F–AVR–09/09 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega164P/324P/644P TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 95 ...
Page 96
... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. ATmega164P/324P/644P 96 COMnx1 ...
Page 97
... See “Register Description” on page 103. Table 13-2 on page 103, and for phase correct PWM refer to (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ATmega164P/324P/644P 103. For fast PWM mode, refer to Table 13-4 on page 104. 121.). 101. ...
Page 98
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast ATmega164P/324P/644P 98 1 ...
Page 99
... MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) 7674F–AVR–09/09 ATmega164P/324P/644P Figure 13-6. The TCNT0 value is in the timing diagram shown as a his- 1 ...
Page 100
... The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. ATmega164P/324P/644P 100 13-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating ...
Page 101
... OCnxPCPWM Figure 13-7 Figure 13-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 ATmega164P/324P/644P 104). The actual OC0x value will only f clk_I/O = -------------------- - N 510 OCnx has a transition from high to low even though Figure 13-7. When the OCR0A value is MAX the ...
Page 102
... Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx ATmega164P/324P/644P 102 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC ...
Page 103
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 98 for more details. shows the COM0A1:0 bit functionality when the WGM02:0 bits are set ATmega164P/324P/644P COM0B0 – ...
Page 104
... Table 13-6 mode. Table 13-6. COM0B1 Note: ATmega164P/324P/644P 104 Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. 1 WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match when up-counting. Set OC0A on 0 Compare Match when down-counting ...
Page 105
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 106
... A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the ATmega164P/324P/644P 106 FOC0A FOC0B – ...
Page 107
... I clk /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R ATmega164P/324P/644P TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R TCNT0 R OCR0A R/W 0 107 ...
Page 108
... Flag Register – TIFR0. 13.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register Bit 0x15 (0x35) Read/Write Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. ATmega164P/324P/644P 108 OCR0B[7:0] R/W ...
Page 109
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 7674F–AVR–09/09 ATmega164P/324P/644P Table 105. 13-8, “Waveform ...
Page 110
... I/O pins, see ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. ATmega164P/324P/644P 110 “Pin Configurations” on page “Register Description” on page 131. “PRR – Power Reduction Register” on page 47 Figure 14-1 ...
Page 111
... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Refer to Figure 1-1 on page 2 and “Alternate Port Functions” on page 77 placement and description. ATmega164P/324P/644P (Note:) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 112
... The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. ATmega164P/324P/644P 112 119.. The compare match event will also set the Compare 240 ...
Page 113
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega164P/324P/644P 113 ...
Page 114
... Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega164P/324P/644P 114 (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ...
Page 115
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. “Timer/Counter Prescaler” on page ATmega164P/324P/644P 153. 115 ...
Page 116
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see ATmega164P/324P/644P 116 shows a block diagram of the counter and its surroundings. ...
Page 117
... TEMP Register. 7674F–AVR–09/09 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega164P/324P/644P Figure 14-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 118
... Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. ATmega164P/324P/644P 118 112. “Accessing 16-bit Registers” ...
Page 119
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega164P/324P/644P 122.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 120
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. ATmega164P/324P/644P 120 112. “Accessing 16-bit Registers” ...
Page 121
... The design of the Output Compare pin logic allows initialization of the OCnx state before the out- put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. The COMnx1:0 bits have no effect on the Input Capture unit. 7674F–AVR–09/09 Waveform Generator I/O See “Register Description” on page 131. ATmega164P/324P/644P Figure 14 OCnx ...
Page 122
... The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. ATmega164P/324P/644P 122 Table 14-2 on page (See “Compare Match Output Unit” on page “ ...
Page 123
... Output mode output is set on compare match and cleared at BOTTOM. 7674F–AVR–09/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I ------------------------------------------------------- OCnA 2 ATmega164P/324P/644P Figure 14-6. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O N OCRnA 1 + 123 ...
Page 124
... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. ATmega164P/324P/644P 124 TOP log ...
Page 125
... The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. 7674F–AVR–09/09 ATmega164P/324P/644P Table on page f clk_I/O f ...
Page 126
... OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord- ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. ATmega164P/324P/644P 126 TOP log ...
Page 127
... The dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 7674F–AVR–09/09 ATmega164P/324P/644P Figure 14-8 f clk_I/O ...
Page 128
... When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. ATmega164P/324P/644P 128 Figure 14-9) ...
Page 129
... Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). 7674F–AVR–09/09 shows the output generated is, in contrast to the phase correct mode, symmetri OCnxPFCPWM Figure 14-10 shows a timing diagram for the setting of OCFnx. ATmega164P/324P/644P f clk_I/O --------------------------------- N TOP therefore shown ...
Page 130
... Figure 14-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. ATmega164P/324P/644P 130 clk I/O ...
Page 131
... TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP COM1A1 COM1A0 COM1B1 R/W R/W R ATmega164P/324P/644P TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 – – WGM11 R/W ...
Page 132
... WGMn3:0 bits setting. when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 14-2. COMnA1/COMnB1 Table 14-3 on page 132 the fast PWM mode. Table 14-3. COMnA1/COMnB1 Note: ATmega164P/324P/644P 132 Table 14-2 on page 132 Compare Output Mode, non-PWM COMnA0/COMnB0 ...
Page 133
... A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. “Phase Correct PWM Mode” on page 125. Table 14-5 on page ATmega164P/324P/644P Description Normal port operation, OCnA/OCnB disconnected. WGMn3 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 134
... When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. ATmega164P/324P/644P 134 (1) WGMn1 ...
Page 135
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B – R/W R ATmega164P/324P/644P – – – – Figure 0 – TCCR1C R 0 135 ...
Page 136
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. ATmega164P/324P/644P 136 7 6 ...
Page 137
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega164P/324P/644P, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 138
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega164P/324P/644P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 139
... BOTTOM Timer/Counter TCNTn = = OCRnA Fixed TOP Value = OCRnB Synchronized Status flags asynchronous mode Status flags ASSRn TCCRnA TCCRnB ATmega164P/324P/644P 2. CPU accessible I/O Registers, includ- 153. “PRR – Power Reduction Register” on TOVn (Int.Req.) clk Tn T/C Oscillator Prescaler clk = 0 OCnA (Int.Req.) Waveform ...
Page 140
... ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see – Asynchronous Status Register” on page “Timer/Counter Prescaler” on page ATmega164P/324P/644P 140 ). T2 See “Output Compare Unit” on page 142. ...
Page 141
... Signalizes that TCNT2 has reached maximum value. Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 145. ATmega164P/324P/644P TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top in the following ...
Page 142
... Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). ATmega164P/324P/644P 142 shows a block diagram of the Output Compare unit. DATA BUS ...
Page 143
... Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. 7674F–AVR–09/09 ATmega164P/324P/644P Figure 15-4 shows a simplified 143 ...
Page 144
... PWM refer to A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. ATmega164P/324P/644P 144 Waveform Generator ...
Page 145
... Figure 15-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period 7674F–AVR–09/09 (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page 1 2 ATmega164P/324P/644P 143.). Table 15-5 on page 145. The counter value OCnx Interrupt Flag Set (COMnx1 149. 145 ...
Page 146
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. ATmega164P/324P/644P 146 f clk_I/O f ...
Page 147
... OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of f ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 7674F–AVR–09/09 ATmega164P/324P/644P ...
Page 148
... COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for the port pin is set as output. ATmega164P/324P/644P 148 15-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating ...
Page 149
... TOVn 7674F–AVR–09/09 f OCnxPCPWM Figure 15-7 on page 148 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 ATmega164P/324P/644P f clk_I/O = -------------------- - N 510 OCnx has a transition from high to low Figure 15-7 on page 148. When the OCR2A value should be replaced by ...
Page 150
... TOVn Figure 15-10 on page 150 Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 15-11 on page 151 ATmega164P/324P/644P 150 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF2A in all modes except CTC mode. ...
Page 151
... OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. 7674F–AVR–09/09 caler (f /8) clk_I/O clk I/O clk Tn /8) I/O TOP - 1 Enable interrupts, if needed. ATmega164P/324P/644P TOP BOTTOM BOTTOM + 1 TOP 151 ...
Page 152
... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. ATmega164P/324P/644P 152 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ...
Page 153
... By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S COM2A1 COM2A0 COM2B1 R/W R/W R ATmega164P/324P/644P 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S for details. /8, clk T2S as well as 0 (stop) may be selected. T2S ...
Page 154
... OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. ATmega164P/324P/644P 154 Table 15-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits ...
Page 155
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. 7674F–AVR–09/09 Table 15-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected ...
Page 156
... Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. ATmega164P/324P/644P 156 Table 15-8. Modes of operation supported by the Timer/Counter Waveform Generation Mode Bit Description ...
Page 157
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select ...
Page 158
... When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. ATmega164P/324P/644P 158 7 ...
Page 159
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 7674F–AVR–09/09 ATmega164P/324P/644P – ...
Page 160
... The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn- chronization Mode” on page 136 for a description of the Timer/Counter Synchronization mode. ATmega164P/324P/644P 160 7 ...
Page 161
... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega164P/324P/644P and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 199. The Power Reduction SPI bit, PRSPI must be written to zero to enable SPI module ...
Page 162
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. ATmega164P/324P/644P 162 Figure 16-2. The sys- ...
Page 163
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 81 direction of the user defined SPI pins. ATmega164P/324P/644P “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 163 ...
Page 164
... SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: ATmega164P/324P/644P 164 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 out ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ...
Page 165
... Read received data and return r16,SPDR in ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 165 ...
Page 166
... CPHA and CPOL. The SPI data transfer formats are shown in 16-3 on page 167 opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 16-2 on page 167 ATmega164P/324P/644P 166 and Figure 16-4 on page 167. Data bits are shifted out and latched in on ...
Page 167
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega164P/324P/644P Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 168
... Refer to marized below: Table 16-3. • Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to functionality is summarized below: Table 16-4. ATmega164P/324P/644P 168 SPIE SPE DORD ...
Page 169
... SPI Data Register. • Bit 5:1 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 170
... Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. ATmega164P/324P/644P 170 7 6 ...
Page 171
... USART1 and USART0 The ATmega164P/324P/644P has two USART’s, USART0 and USART1. The functionality for all USART’s is described below, most register and bit references in this sec- tion are written in general form. A lower case “n” replaces the USART number. ...
Page 172
... The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATmega164P/324P/644P 172 (1) UBRR[H:L] ...
Page 173
... DDR_XCK UCPOL Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). OSC ATmega164P/324P/644P U2X / DDR_XCK 0 ...
Page 174
... For the Transmitter, there are no downsides. ATmega164P/324P/644P 174 contains equations for calculating the baud rate (in bits per second) and ...
Page 175
... Figure 17-2 on page 173 depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 17-3 on page 175 ATmega164P/324P/644P for details. f OSC f ---------- - XCK 4 Sample Sample shows, when UCPOLn is zero the data will ...
Page 176
... USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. ATmega164P/324P/644P 176 illustrates the possible combinations of the frame formats. Bits inside ...
Page 177
... The baud rate is given as a function parameter. 7674F–AVR–09/ even n 1 – odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega164P/324P/644P 177 ...
Page 178
... USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If syn- chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. ATmega164P/324P/644P 178 (1) ; Set baud rate ...
Page 179
... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data UDRn,r16 out ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 179 ...
Page 180
... This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. ATmega164P/324P/644P 180 (1)(2) ...
Page 181
... When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. 7674F–AVR–09/09 ATmega164P/324P/644P 181 ...
Page 182
... UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. ATmega164P/324P/644P 182 (1) ; Wait for data to be received ...
Page 183
... UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 183 ...
Page 184
... The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see ATmega164P/324P/644P 184 “Parity Bit Calculation” on page 177 and “ ...
Page 185
... UCSRnA, RXCn ret r16, UDRn in rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 185 ...
Page 186
... If two or all three samples have high levels, the received bit is registered logic 1. If two or all three samples have low levels, the received bit is registered logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. ATmega164P/324P/644P 186 RxD ...
Page 187
... Middle sample number used for majority voting for Double Speed mode the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. ATmega164P/324P/644P STOP 1 (A) ( ...
Page 188
... CPU system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn setting, but has to be used differently when part of a system utilizing the Multi-processor Communication mode. ATmega164P/324P/644P 188 and Table 17-3 on page 188 ...
Page 189
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 7674F–AVR–09/09 ATmega164P/324P/644P 189 ...
Page 190
... The TXCn Flag bit is auto- matically cleared when a transmit complete interrupt is executed can be cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see description of the TXCIEn bit). ATmega164P/324P/644P 190 7 6 ...
Page 191
... RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set. 7674F–AVR–09/09 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega164P/324P/644P 188 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 191 ...
Page 192
... Must be written before writing the low bits to UDRn. 17.11.4 UCSRnC – USART Control and Status Register n C Bit Read/Write Initial Value • Bits 7:6 – UMSELn1:0 USART Mode Select These bits select the mode of operation of the USARTn as shown in Table 17-4. UMSELn1 ATmega164P/324P/644P 192 UMSELn1 UMSELn0 UPMn1 UPMn0 R/W ...
Page 193
... USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit UCSZn Bits Settings UCSZn1 ATmega164P/324P/644P Mode Synchronous USART (Reserved) (1) Master SPI (MSPIM) for full description of the Master SPI Mode (MSPIM) Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 ...
Page 194
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega164P/324P/644P 194 UCSZn Bits Settings ...
Page 195
... ATmega164P/324P/644P Table 17-9 Closest Match – 100% BaudRate f = 2.0000 MHz osc U2Xn = 1 U2Xn = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 0. ...
Page 196
... Max. 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% ATmega164P/324P/644P 196 f = 4.0000 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0. ...
Page 197
... Mbps 691.2 kbps ATmega164P/324P/644P MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0. ...
Page 198
... Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max. 1. ATmega164P/324P/644P 198 (Continued) U2Xn = 0 UBRR Error 416 207 103 Mbps UBRR = 0, Error = 0. ...
Page 199
... Table 18-1: Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Rate BAUD = -------------------------------------- - 2 UBRRn 1. The baud rate is defined to be the transfer rate in bit per second (bps) ATmega164P/324P/644P Equation for Calculating UBRRn (1) Value f OSC UBRRn = + 1 f OSC ------------------- - 1 – ...
Page 200
... When a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. ATmega164P/324P/644P 200 Baud rate (in bits per second, bps) System Oscillator clock frequency ...