ATTINY167-15MD Atmel, ATTINY167-15MD Datasheet - Page 47
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ATTINY167-15MD
Manufacturer Part Number
ATTINY167-15MD
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MD
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5.9.2
5.9.3
7728G–AVR–06/10
MCUCR – MCU Control Register
PRR – Power Reduction Register
Table 5-2.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before
the execution of the SLEEP instruction and to clear it immediately after waking up.
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
on page
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must
first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be
set to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD dis-
able is controlled by a timed sequence.
• Bit 7 - Res: Reserved bit
This bit is reserved in ATtiny87/167 and will always read as zero.
• Bit 6 - Res: Reserved bit
This bit is reserved in ATtiny87/167 and will always read as zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SM1
0
0
1
1
42. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
Sleep Mode Select
R
7
–
0
R
7
–
0
SM0
0
1
0
1
BODS
R/W
6
0
R
6
–
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
BODSE
PRLIN
R/W
R/W
5
0
5
0
PRSPI
R/W
PUD
R/W
4
0
4
0
PRTIM1
R/W
3
0
R
3
–
0
ATtiny87/ATtiny167
PRTIM0
R/W
2
0
R
2
–
0
PRUSI
R/W
R
1
–
0
1
0
PRADC
R
0
–
0
R/W
0
0
Table 5-1
MCUCR
PRR
47
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