ATTINY167-15MD Atmel, ATTINY167-15MD Datasheet - Page 69
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ATTINY167-15MD
Manufacturer Part Number
ATTINY167-15MD
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MD
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.2.2
9.2.3
9.2.4
7728G–AVR–06/10
Toggling the Pin
Break-Before-Make Switching
Switching Between Input and Output
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port.
In the Break-Before-Make mode when switching the DDRxn bit from input to output an imme-
diate tri-state period lasting one system clock cycle is introduced as indicated in
For example, if the system clock is 4 MHz and the DDRxn is written to make an output, the
immediate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the
port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is
two system clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the
port-wise BBMx enable bits. For further information about the BBMx bits, see
Register – PORTCR” on page
no immediate tri-state period introduced.
Figure 9-3.
YSTEM CLOCK
NSTRUCTIONS
W h e n s w i t c h i n g b e t w e e n t r i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) a n d o u t p u t h i g h
( { D D x n , P O R T x n } = 1 , 1 ) , a n i n t e r m e d i a t e s t a t e w i t h e i t h e r p u l l - u p e n a b l e d
{DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the
pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the
MCUCR Register or the PUDx bit in PORTCR Register can be set to disable all pull-ups in the
port.
Switching between input with pull-up and output low generates the same problem. The user
m u s t u s e e it h e r t h e tr i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) o r th e o u t p u t h i g h s t a t e
({DDxn, PORTxn} = 1, 1) as an intermediate step.
PORTx
DDRx
R 16
R 17
Px0
Px1
Break Before Make, switching between input and output
out DDRx, r16
0x01
75. When switching the DDRxn bit from output to input there is
tri-state
immediate tri-state cycle
0x02
0x01
0x55
0x02
nop
tri-state
ATtiny87/ATtiny167
out DDRx, r17
immediate tri-state cycle
0x01
tri-state
“Port Control
Figure
9-3.
69
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