AT91SAM7S32-AU-999 Atmel, AT91SAM7S32-AU-999 Datasheet - Page 637
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AT91SAM7S32-AU-999
Manufacturer Part Number
AT91SAM7S32-AU-999
Description
IC MCU ARM7 32KB FLASH 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S32-AU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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40.8.2
40.8.2.1
40.8.3
40.8.3.1
40.8.3.2
40.8.4
40.8.4.1
6175K–ATARM–30-Aug-10
Non Volatile Memory Bits (NVM Bits)
Parallel Input/Output Controller (PIO)
Pulse Width Modulation Controller (PWM)
NVM Bits: Write/Erase Cycles Number
PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31
PIO: Drive Low NRST, PA0-PA16 and PA21-PA31
PWM: Update when PWM_CCNTx = 0 or 1
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 256 KB Flash memory, it
remains at 10K for the Flash memory.
None.
When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the volt-
age of the I/O stabilizes at VPull-up.
Vpull-up
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at
3.3 V and 25 µA at 1.8V.
I Leakage
It is recommended to use an external pull-up if needed.
When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driv-
ing the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical
zero.
Output impedance must be lower than 500 ohms.
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Check the Channel Counter Register before writing the update register.
VPull-up Min
VDDIO - 0.65 V
Parameter
I Leakage at 3,3V
I Leakage at 1.8V
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
VPull-up Max
VDDIO - 0.45 V
Typ
2.5
1
µA
µA
Max
45
25
AT91SAM7S Series Preliminary
µA
µA
637
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