Z86E4312PSC Zilog, Z86E4312PSC Datasheet - Page 44

IC MICROCONTROLLER 4K 40-DIP

Z86E4312PSC

Manufacturer Part Number
Z86E4312PSC
Description
IC MICROCONTROLLER 4K 40-DIP
Manufacturer
Zilog
Series
Z8®r
Datasheet

Specifications of Z86E4312PSC

Core Processor
Z8
Core Size
8-Bit
Speed
12MHz
Connectivity
EBI/EMI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
236 x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.620", 15.75mm)
For Use With
309-1034 - ADAPTER 40-DIP ZIF TO 44-QFP309-1033 - ADAPTER 40-DIP TO 44-QFP309-1030 - ADAPTER 40-DIP TO 44-PLCC309-1029 - ADAPTER 40-DIP ZIF TO 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
269-1037
PS022901-0508
OEN
Out
In
Open-Drain
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS-compatible port with multi-
plexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be pro-
grammed as inputs or outputs or can be configured under software control as an Address/
Data port for interfacing external memory. The input buffers are Schmitt-triggered and the
output buffers can be globally programmed as either push-pull or open-drain. Low EMI
output buffers can be globally programmed by the software. Port 1 can be placed under
handshake control. In this configuration, Port 3, lines P33 and P34 are used as the hand-
shake controls RDY1 and DAV1 (Ready and Data Available). To interface external mem-
ory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256
external locations are required, Port 0 outputs the additional lines (see
1.5
MCU
2.3 Hysteresis V
Figure 18. Port 0 Configuration
4
4
CC
R ~ ~ 500 KΩ
@ V
Handshake Controls
DAV0 and RDY0
(P32 and P35)
Port 0 (I/O)
CC
= 5.0V
CMOS Z8
®
Product Specification
Auto Latch
OTP Microcontrollers
Electrical Characteristics
Figure
PAD
19).
40

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