Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 132

• Manufacturer Part Number: Z8F6401AN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401AN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401AN020SC00T

PS017609-0803
Writing a Transaction with a 10-Bit Address
S
Slave Address
14. Software responds by setting the STOP bit of the I
15. If no new data is to be sent or address is to be sent, software responds by clearing the
16. The I
17. The I
1. The I
2. The I
3. If the slave needs to service an interrupt, it pulls the SCL signal low, which halts I
4. If there is no other data in the I
The data transfer format for a 10-bit addressed slave is illustrated in the figure below.
Shaded regions indicate data transferred from the I
regions indicate data transferred from the slaves to the I
Figure 80. 10-Bit Addressed Slave Data Transfer Format
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write signal. The transmit operation is carried out in the same manner as 7-bit addressing.
The data transfer format for a transmit operation on a 10-bit addressed slave is as follows:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing the first slave address byte. The least-
5. Software asserts the START bit of the I
6. The I
1st 7 bits
TXI bit of the I
signal Low). If the slave pulls the SDA signal High (Not-Acknowledge), the I
Controller sends a Stop signal.
operation.
register is set by software, then the Stop signal is sent.
significant bit must be 0 for the write operation.
2
2
2
2
2
2
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP condition to the I
C Controller shifts the I
C Controller waits for the slave to send an Acknowledge (by pulling the SDA
C interrupt asserts because the I
C Controller sends the START condition to the I
W=0
2
C Control register.
A
Slave Address
2nd Byte
2
2
C Shift register out onto SDA signal.
C Data register or the STOP bit in the I
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
2
2
C Control register.
C Control register to enable Transmit interrupts.
2
C Data register is empty.
2
C Control register.
A
2
11110XX
C Controller to slaves and unshaded
Data
2
C Control register.
2
C Controller.
2
C bus.
2
C slave.
. The two bits
A
Data
XX
2
Z8 Encore!
C Control
I2C Controller
are the two
A/A
2
C
2
P
C
®
114