Z8F012ASJ020EG Zilog, Z8F012ASJ020EG Datasheet - Page 91

• Manufacturer Part Number: Z8F012ASJ020EG
• Description: IC ENCORE XP MCU FLASH 1K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4042; Z8F012ASJ020EG

PS022825-0908
Follow the steps below for configuring a timer for COMPARE mode and initiating the
count:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
5. If using the Timer Output function, configure the associated GPIO port pin for the
6. Write to the Timer Control register to enable the timer and initiate counting.
In COMPARE mode, the system clock always provides the timer input. The Compare time
can be calculated by the following equation:
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
Follow the steps below for configuring a timer for GATED mode and initiating the count:
1. Write to the Timer Control register to:
–
–
–
–
to the relevant interrupt registers.
Timer Output alternate function.
–
–
–
COMPARE Mode Time (s)
0001H
Disable the timer.
Configure the timer for COMPARE mode.
Set the prescale value.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate.
Disable the timer.
Configure the timer for GATED mode.
Set the prescale value.
and counting resumes (assuming the Timer Input signal remains asserted).
=
(
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Compare Value Start Value
System Clock Frequency (Hz)
–
Z8 Encore! XP
Product Specification
)
×
Prescale
®
F082A Series
Timers
80