MC68HC11K1CFN4 Freescale Semiconductor, MC68HC11K1CFN4 Datasheet - Page 47

• Manufacturer Part Number: MC68HC11K1CFN4
• Description: IC MCU 640 EEPROM 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

PORTG —Port G Data
DDRG —Data Direction Register for Port G
DDG[7:0] —Data Direction for Port G
PGAR — Port G Assignment
Bits [7:6] —Not implemented
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
M68HC11 K Series
MC68HC11KTS/D
RESET:
RESET:
RESET:
Alt. Pin
$002D
Func.:
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W. Refer to PGAR register description.
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero. Refer to PGAR register description.
Always read zero
0 = Configure corresponding I/O pin for input only
1 = Configure corresponding I/O pin for output
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is memory expansion address line (XA[18:13])
DDG7
Bit 7
PG7
R/W
Bit 7
Bit 7
—
0
0
I
In expanded and special test modes, chip-select circuitry forces the I/O state to be
an output for each port H pin associated with an enabled chip select. In any mode,
PWM circuitry forces the I/O state to be an output for each port H line associated
with an enabled pulse width modulator channel. In these cases, data direction bits
are not changed and have no effect on these lines. DDRH reverts to controlling the
I/O state of a pin when the associated function is disabled. Refer to 4.3 Memory
Expansion and Chip Selects and 12 Pulse-Width Modulation Timer for further
information.
Each PGAR bit forces the I/O state to be an output for each port G pin associated
with an enabled expansion address line. In this case, data direction bits are not
changed and have no effect on these lines. DDRG reverts to controlling the I/O
state of a pin when the associated function is disabled. Refer to 4.1 Memory Ex-
pansion for further information.
DDG6
PG6
—
—
6
6
0
6
0
I
Freescale Semiconductor, Inc.
For More Information On This Product,
PGAR5
DDG5
XA18
PG5
5
5
0
5
0
I
Go to: www.freescale.com
PGAR4
DDG4
XA17
PG4
4
4
0
4
0
I
NOTE
NOTE
PGAR3
DDG3
XA16
PG3
0
0
3
3
3
I
PGAR2
DDG2
XA15
PG2
2
2
0
2
0
I
PGAR1
DDG1
XA14
PG1
1
1
0
1
0
I
PGAR0
DDG0
$002D
$007E
XA13
$007F
Bit 0
PG0
Bit 0
Bit 0
0
0
I
MOTOROLA
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