MC68HC908QY2CP Freescale Semiconductor, MC68HC908QY2CP Datasheet - Page 137
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MC68HC908QY2CP
Manufacturer Part Number
MC68HC908QY2CP
Description
IC MCU 1.5K FLASH W/ADC 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QY4MDWER.pdf
(184 pages)
Specifications of MC68HC908QY2CP
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908QY2CPE
Manufacturer:
FREESCALE
Quantity:
7 762
- Current page: 137 of 184
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15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
BDCOP — Break Disable COP Bit
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
Freescale Semiconductor
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Address: $FE02
Address: $FE00
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit 7
Bit 7
R
R
0
0
Figure 15-6. Break Auxiliary Register (BRKAR)
= Unimplemented
= Reserved
Figure 15-7. Break Status Register (BSR)
MC68HC908QY/QT Family Data Sheet, Rev. 6
0
R
6
0
6
R
5
0
0
5
R
4
0
0
4
1. Writing a 0 clears SBSW.
R
3
0
0
3
R
2
0
0
2
Note
SBSW
1
0
0
1
0
(1)
BDCOP
Bit 0
Bit 0
Break Module (BRK)
R
0
137
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