MC68HC908GR8CDW Freescale Semiconductor, MC68HC908GR8CDW Datasheet - Page 65

• Manufacturer Part Number: MC68HC908GR8CDW
• Description: IC MCU 8K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.3.4 SIM Reset Status Register
MC68HC908GR8 — Rev 4.0
MOTOROLA
NOTE:
Address:
This read-only register contains flags to show reset sources. All flag bits
are automatically cleared following a read of the register. Reset service
can read the SIM reset status register to clear the register after power-
on reset and to determine the source of any subsequent reset.
The register is initialized on powerup as shown with the POR bit set and
all other bits cleared. During a POR or any other internal reset, the RST
pin is pulled low. After the pin is released, it will be sampled 32 XCLK
cycles later. If the pin is not above a V
the SRSR may be set in addition to whatever other bits are set.
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register,
multiple flags remain set.
POR — Power-On Reset Flag
PIN — External Reset Flag
COP — Computer Operating Properly Reset Bit
Read:
Write:
POR:
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
$FE01
POR
Bit 7
1
Figure 4-3. SIM Reset Status Register (SRSR)
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Resets and Interrupts
= Unimplemented
PIN
6
0
COP
5
0
ILOP
4
0
IH
at that time, then the PIN bit in
ILAD
3
0
2
0
0
Resets and Interrupts
LVI
1
0
Technical Data
Bit 0
Resets
0
0
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