COP8CFE9IMT9/NOPB National Semiconductor, COP8CFE9IMT9/NOPB Datasheet - Page 21
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COP8CFE9IMT9/NOPB
Manufacturer Part Number
COP8CFE9IMT9/NOPB
Description
IC MCU EEPROM 8BIT 8K 48-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Cr
Datasheet
1.COP8-EMFA-28N.pdf
(63 pages)
Specifications of COP8CFE9IMT9/NOPB
Core Processor
COP8
Core Size
8-Bit
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
39
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Eeprom Size
-
Other names
*COP8CFE9IMT9
*COP8CFE9IMT9/NOPB
COP8CFE9IMT9
*COP8CFE9IMT9/NOPB
COP8CFE9IMT9
5.0 In-System Programming
5.3.2 ISP Read Data Register
The Read Data Register (ISPRD) contains the value read
back from a read operation. This register can be accessed
from either flash program memory or Boot ROM. This regis-
ter is undefined on Reset.
5.3.3 ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be
written into the specified address. This register is undeter-
mined on Reset. This register can be accessed from either
flash program memory or Boot ROM. The Write Data register
must be maintained for the entire duration of the operation.
(Continued)
Bit 7
Bit7
R
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
Bit6
TABLE 7. ISP Read Data Register
R/W
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Bit 5
Bit5
Bit 4
Bit4
R/W
5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
ISPRD
Bit 3
Bit3
R/W
Bit 2
Bit2
4
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
1
Register Bit
TABLE 9. PGMTIM Register Format
Bit 1
Bit1
R/W
3
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
0
1
1
Bit 0
Bit0
PGMTIM
R/W
21
2
0
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
5.3.4 ISP Write Timing Register
The Write Timing Register (PGMTIM) is used to control the
width of the timing pulses for write and erase operations. The
value to be written into this register is dependent on the
frequency of CKI and is shown in Table 9 . This register must
be written before any write or erase operation can take
place. It only needs to be loaded once, for each value of CKI
frequency. This register can be loaded from either flash
program memory or Boot ROM and must be maintained for
the entire duration of the operation. The MICROWIRE/PLUS
ISP routine that is resident in the boot ROM requires that this
Register be defined prior to any access to the Flash memory.
Refer to 5.7 MICROWIRE/PLUS ISP for more information on
available ISP commands. On Reset, the PGMTIM register is
loaded with the value that corresponds to 10 MHz frequency
for CKI.
Bit 7
Bit7
R/W
Bit 6
Bit6
1
0
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
1
1
TABLE 8. ISP Write Data Register
Bit 5
Bit5
R/W
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
Bit 4
Bit4
ISPWR
Bit 3
Bit3
CKI Frequency Range
200 kHz–266.67 kHz
500 kHz–666.67 kHz
800 kHz–1.067 MHz
1.125 MHz–1.5 MHz
2.625 MHz–3.5 MHz
112.5 kHz–150 kHz
62.5 kHz–83.3 kHz
3.5 MHz–4.67 MHz
50 kHz–66.67 kHz
100 kHz–133 kHz
150 kHz–200 kHz
225 kHz–300 kHz
300 kHz–400 kHz
375 kHz–500 kHz
600 kHz–800 kHz
25 kHz–33.3 kHz
37.5 kHz–50 kHz
1 MHz–1.33 MHz
2 MHz–2.67 MHz
7.5 MHz–10 MHz
75 kHz–100 kHz
1.5 MHz–2 MHz
4.5 MHz–6 MHz
6 MHz–8 MHz
Bit 2
Bit2
Bit 1
Bit1
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Bit 0
Bit0