MC68HC908GZ8MFJ Freescale Semiconductor, MC68HC908GZ8MFJ Datasheet - Page 233

• Manufacturer Part Number: MC68HC908GZ8MFJ
• Description: IC MCU 8K FLASH 8MHZ CAN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8MFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.4 Functional Description
Figure 17-2
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt
driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. See
13.5.3 Port C Input Pullup Enable
The following paragraphs describe the operation of the SPI module.
17.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
Freescale Semiconductor
Addr.
$0010
$0011
$0012
17.13.2 SPI Status and Control
SPI Status and Control
Register Name
summarizes the SPI I/O registers and
SPI Control Register
Register (SPSCR)
SPI Data Register
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See
See page 247.
See page 249.
See page 250.
(SPCR)
(SPDR)
Reset:
Reset:
Reset:
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Read:
Read:
Read:
Write:
Write:
Write:
Figure 17-2. SPI I/O Register Summary
Register.
SPRIE
SPRF
Bit 7
R7
T7
R
0
0
Register.) Through the SPSCK pin, the baud rate generator of the
= Reserved
ERRIE
Figure
R6
T6
R
6
0
0
NOTE
Figure 17-3
SPMSTR
17-4.
17.13.1 SPI Control
OVRF
R5
T5
5
1
0
MODF
CPOL
Unaffected by reset
shows the structure of the SPI module.
R4
T4
4
0
0
= Unimplemented
CPHA
SPTE
R3
T3
3
1
1
Register.
MODFEN
SPWOM
R2
T2
2
0
0
Functional Description
SPR1
SPE
R1
T1
1
0
0
SPTIE
SPR0
Bit 0
R0
T0
0
0
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