MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 159

• Manufacturer Part Number: MC68HC908GR16VFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16VFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.4.3.7 Receiver Interrupts
These sources can generate CPU interrupt requests from the ESCI receiver:
14.4.3.8 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
14.5.1 Wait Mode
The ESCI module remains active in wait mode. Any enabled CPU interrupt request from the ESCI module
can bring the MCU out of wait mode.
If ESCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Freescale Semiconductor
2. Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
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receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit
or after the stop bit.
ESCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the ESCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive 1s shifted in from the
RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU
interrupt requests.
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate ESCI error CPU interrupt requests.
Noise flag (NF) — The NF bit is set when the ESCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate ESCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop
bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate ESCI error CPU
interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the ESCI detects a parity error in incoming
data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate ESCI error CPU
interrupt requests.
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle will cause the receiver to wakeup.
MC68HC908GR16 Data Sheet, Rev. 5.0
NOTE
Low-Power Modes
159