MC68HC908JB12JDW Freescale Semiconductor, MC68HC908JB12JDW Datasheet - Page 157

• Manufacturer Part Number: MC68HC908JB12JDW
• Description: IC MCU 12K FLASH 6MHZ USB 20SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB12JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

MC68HC908JB16
Freescale Semiconductor
—
Rev. 1.1
CHxIE — Channel x Interrupt Enable Bit
CH01IE — CH0F and CH1F Interrupt Enable Bit
MS0B — Mode Select Bit B
MSxA — Mode Select Bit A
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIM channel x status and control register with CHxF
set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0
to CHxF has no effect. Therefore, an interrupt request cannot be lost
due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on
channel x.
Reset clears the CHxIE bit.
This read/write bit enables TIM CPU interrupt service requests when
CH0F and CH1F are set.
Reset clears the CH01IE bit.
This read/write bit selects buffered output compare/PWM operation.
MS0B exists only in the TIM1 channel 0 and TIM2 channel 0 status
and control registers.
Setting MS0B disables the channel 1 status and control register.
Reset clears the MS0B bit.
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input
capture operation or unbuffered output compare/PWM operation.
See
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = CPU interrupt requests when CH0F and CH1F are set
0 = No CPU interrupt requests when CH0F and CH1F are set
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
Table
Timer Interface Module (TIM)
10-3.
Timer Interface Module (TIM)
Technical Data
157