C8051F300 Silicon Laboratories Inc, C8051F300 Datasheet - Page 165

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C8051F300

Manufacturer Part Number
C8051F300
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Datasheets

Specifications of C8051F300

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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17.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging, FLASH program-
ming, and boundary scan functions may be performed. This is possible because C2 communication is typically per-
formed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted
state, the C2 interface can safely ‘borrow’ the C2CK (normally /RST) and C2D (normally P0.7) pins. In most appli-
cations, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation con-
figuration is shown in Figure 17.6.
The configuration in Figure 17.6 assumes the following:
Additional resistors may be necessary depending on the specific application.
1.
2.
The user input (b) cannot change state while the target device is halted.
The /RST pin on the target device is used as an input only.
/Reset (a)
Output (c)
Input (b)
Figure 17.6. Typical C2 Pin Sharing
Rev. 2.3
C8051F300/1/2/3/4/5
C8051F300
C2CK (/RST)
C2D (P0.7)
165

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