C8051F019 Silicon Laboratories Inc, C8051F019 Datasheet - Page 49
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C8051F019
Manufacturer Part Number
C8051F019
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
16 bit
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
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Part Number
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Company:
Part Number:
C8051F019
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Part Number:
C8051F019-GQ
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Silicon Laboratories Inc
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C8051F019-GQR
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Company:
Part Number:
C8051F019R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
8.2.
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two
separate memory spaces: program memory and data memory. Program and data memory share the same address
space but are accessed via different instruction types. There are 256 bytes of internal data memory and 64K bytes of
internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is
shown in Figure 8.2.
8.2.1.
The CIP-51 has a 64K-byte program memory space. The MCU implements 16k + 128 bytes of this program
memory space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses
0x0000 to 0x3FFF. Note: 512 bytes (0x3E00 – 0x3FFF) of this memory are reserved for factory use and are not
available for user program storage. The 128 byte block is located at addresses 0x8000 – 0x807F.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by
setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a
mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage.
Refer to Section 9 (Flash Memory) for further details.
8.2.2.
The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct
or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are
addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next
16 bytes, locations 0x20 through 0x2F, may be addressed as bytes or as 128 bit locations accessible with the direct-
bit addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same
address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The
addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses
the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR
space. Instructions using indirect addressing above 0x7F will access the upper 128 bytes of data memory. Figure
8.2 illustrates the data memory organization of the CIP-51.
The C8051F018/9 also have 1024 bytes of RAM in the external data memory space of the CIP-51, accessible using
the MOVX instruction. Refer to Section 10 (External RAM) for details.
8.2.3.
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-
purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these
banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the
active register bank (see description of the PSW in Figure 8.6). This allows fast context switching when entering
subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
49
C8051F018
C8051F019
MEMORY ORGANIZATION
Program Memory
Data Memory
General Purpose Registers
Rev. 1.2