MC68HC711E20CFN4 Freescale Semiconductor, MC68HC711E20CFN4 Datasheet - Page 124

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MC68HC711E20CFN4

Manufacturer Part Number
MC68HC711E20CFN4
Description
IC MCU 20K OTP 4MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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MSTR — Master Mode Select Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPR[1:0] — SPI Clock Rate Select Bits
8.7.2 Serial Peripheral Status Register
SPIF — SPI Interrupt Complete Flag
WCOL — Write Collision Bit
124
Serial Peripheral Interface (SPI)
It is customary to have an external pullup resistor on lines that are driven by open-drain devices.
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master
device has a steady state low value. When CPOL is set, SCK idles high. Refer to
Clock Phase and Polarity
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to
and
These two bits select the SPI clock (SCK) rate when the device is configured as master. When the
device is configured as slave, these bits have no effect. Refer to
SPIF is set upon completion of data transfer between the processor and the external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit, read the
SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first, attempts to
write SPDR are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access
of SPDR. Refer to
0 = Slave mode
1 = Master mode
0 = No write collision
1 = Write collision
8.4 Clock Phase and Polarity
SPR[1:0]
Address:
0 0
0 1
1 0
1 1
Reset:
Read:
Write:
8.5.4 Slave Select
E Clock By
$1029
SPIF
Bit 7
Figure 8-4. Serial Peripheral Status Register (SPSR)
Divide
0
16
32
2
4
Controls.
= Unimplemented
WCOL
6
0
M68HC11E Family Data Sheet, Rev. 5.1
Frequency at
E = 1 MHz
Controls.
62.5 kHz
31.3 kHz
Table 8-1. SPI Clock Rates
500 kHz
250 kHz
(Baud)
and
5
0
8.6 SPI System
MODF
Frequency at
4
0
E = 2 MHz
62.5 kHz
1.0 MHz
500 kHz
125 kHz
(Baud)
3
0
Errors.
Frequency at
E = 3 MHz (
187.5 kHz
93.8 kHz
1.5 MHz
750 kHz
Table
Baud)
2
0
8-1.
1
0
Frequency at
E = 4 MHz
250 kHz
125 kHz
(Baud)
2 MHz
1 MHz
Freescale Semiconductor
Figure 8-2
Bit 0
0
Figure 8-2
and
8.4

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