MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 161

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MC68HC711P2CFN4

Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711P2CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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8.8.2 PACNT — Pulse accumulator count register
8.8.3 Pulse accumulator status and interrupt bits
8.8.3.1 TMSK2 — Timer interrupt mask 2 register
8.8.3.2 TFLG2 — Timer interrupt flag 2 register
MC68HC11P2 — Rev 1.0
Timer interrupt mask 2 (TMSK2) $0024
Timer interrupt flag 2 (TFLG2)
Pulse accumulator count
(PACNT)
This 8-bit read/write register contains the count of external input events
at the PAI input, or the accumulated count. In gated time accumulation
mode, PACNT is readable even if PAI is not active. The counter is not
affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading
occur during opposite half cycles.
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF
are located within timer registers TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse accumulator interrupt enable and overflow
flag
Freescale Semiconductor, Inc.
The PAOVF status bit is set each time the pulse accumulator count
rolls over from $FF to $00. To clear this status bit, write a one in the
corresponding data bit position (bit 5) of the TFLG2 register. The
PAOVI control bit allows configuring the pulse accumulator overflow
Address bit 7
Address bit 7
Address bit 7
For More Information On This Product,
$0025
$0027 (bit 7)
Go to: www.freescale.com
TOF
TOI
Timing System
RTIF PAOVF PAIF
bit 6
bit 6
RTII PAOVI PAII
bit 6
(6)
bit 5
bit 5
bit 5
(5)
bit 4
bit 4
bit 4
(4)
bit 3
bit 3
bit 3
(3)
0
0
bit 2
bit 2
bit 2
(2)
0
0
bit 1
bit 1
PR1
bit 1
(1)
0
Pulse accumulator
(bit 0) undefined
bit 0
bit 0
PR0 0000 0000
bit 0
0
Technical Data
Timing System
0000 0000
on reset
on reset
on reset
State
State
State

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