MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 217

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.3.5 Program counter (PC)
MC68HC11P2 — Rev 1.0
When a subroutine is called by a jump to subroutine (JSR) or branch to
subroutine (BSR) instruction, the address of the instruction after the JSR
or BSR is automatically pushed onto the stack, less significant byte first.
When the subroutine is finished, a return from subroutine (RTS)
instruction is executed. The RTS pulls the previously stacked return
address from the stack, and loads it into the program counter. Execution
then continues from this recovered return address.
When an interrupt is recognized, the current instruction finishes
normally, the return address (the current value in the program counter)
is pushed onto the stack, all of the CPU registers are pushed onto the
stack, and execution continues at the address specified by the vector for
the interrupt. At the end of the interrupt service routine, an RTI instruction
is executed. The RTI instruction causes the saved registers to be pulled
off the stack in reverse order. Program execution resumes at the return
address.
There are instructions that push and pull the A and B accumulators and
the X and Y index registers. These instructions are often used to
preserve program context. For example, pushing accumulator A onto the
stack when entering a subroutine that uses accumulator A, and then
pulling accumulator A off the stack just before leaving the subroutine,
ensures that the contents of a register will be the same after returning
from the subroutine as they were before starting the subroutine.
The program counter, a 16-bit register, contains the address of the next
instruction to be executed. After reset, the program counter is initialized
from one of six possible vectors, depending on operating mode and the
cause of reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
Normal
CPU Core and Instruction Set
Go to: www.freescale.com
POR or RESET pin
Table 11-1. Reset vector comparison
$FFFE, $FFFF
Clock monitor
$FFFC, $FFFD
CPU Core and Instruction Set
COP watchdog
$FFFA, $FFFB
Technical Data
Registers