MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 264
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MC9S12E128CFU
Manufacturer Part Number
MC9S12E128CFU
Description
IC MCU 128K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12E128CFU
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 8 Serial Communication Interface (SCIV3)
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register
continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE
to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use this sequence between messages:
8.4.4.3
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift
register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit.
Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at
logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software
clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least
one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit
of the next frame.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers:
8.4.4.4
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character
length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle
character that begins the first transmission initiated after writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the frame currently being transmitted.
264
1. Write the last byte of the first message to SCIDRH/L.
2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCIDRH/L.
•
•
•
•
register.
Sets the framing error flag, FE
Sets the receive data register full flag, RDRF
Clears the SCI data registers (SCIDRH/L)
May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF
(see
2
(SCISR2)”).
Section 8.3.2.4, “SCI Status Register 1 (SCISR1)”
Break Characters
Idle Characters
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out through the TXD pin. Setting TE after the
stop bit appears on TXD causes data previously written to the SCI data
register to be lost. Toggle the TE bit for a queued idle character while the
MC9S12E128 Data Sheet, Rev. 1.07
NOTE
and
Section 8.3.2.5, “SCI Status Register
Freescale Semiconductor
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