MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 533
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MC9S12E128CFU
Manufacturer Part Number
MC9S12E128CFU
Description
IC MCU 128K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12E128CFU
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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18.3.2.13 Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to
this register have no effect.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
18.3.2.14 IRQ Control Register (IRQCR)
Read: See individual bit descriptions below
Write: See individual bit descriptions below
Freescale Semiconductor
IRQEN
Field
IRQE
7
6
Reset
Reset
W
W
R
R
IRQ Select Edge Sensitive Only
Special modes: read or write anytime
Normal and Emulation modes: read anytime, write once
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
External IRQ Enable
Normal, emulation, and special modes: read or write anytime
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
Note: When IRQEN = 0, the edge detect latch is disabled.
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
IRQE
7
0
0
7
0
= Unimplemented or Reserved
= Unimplemented or Reserved
IRQEN
6
0
0
6
1
Figure 18-18. IRQ Control Register (IRQCR)
Table 18-12. IRQCR Field Descriptions
Figure 18-17. Reserved Register
MC9S12E128 Data Sheet, Rev. 1.07
5
0
0
5
0
0
0
0
0
0
Description
4
4
Chapter 18 Multiplexed External Bus Interface (MEBIV3)
0
0
0
0
3
3
0
0
0
0
2
2
0
0
0
0
1
1
0
0
0
0
0
0
533
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