HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 17
![IC H8 MCU FLASH 32K 64QFP](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
HD64F3664H
Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664H
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3664H H8/3664
Manufacturer:
RENESAS
Quantity:
13
Company:
Part Number:
HD64F3664HJ
Manufacturer:
TI
Quantity:
171
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F3664HV
Manufacturer:
ALTERA
Quantity:
101
Company:
Part Number:
HD64F3664HV
Manufacturer:
RENESAS
Quantity:
630
Company:
Part Number:
HD64F3664HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 17 of 446
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Section 15 I
15.1
15.2
15.3
15.4
15.5
Section 16 A/D Converter..................................................................................275
16.1
16.2
16.3
16.4
16.5
16.6
14.8.4
Features............................................................................................................................. 233
Input/Output Pins.............................................................................................................. 235
Register Descriptions........................................................................................................ 236
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
15.3.7
Operation .......................................................................................................................... 249
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.4.9
Usage Notes ...................................................................................................................... 266
Features............................................................................................................................. 275
Input/Output Pins.............................................................................................................. 277
Register Description ......................................................................................................... 278
16.3.1
16.3.2
16.3.3
Operation .......................................................................................................................... 281
16.4.1
16.4.2
16.4.3
16.4.4
A/D Conversion Accuracy Definitions ............................................................................. 284
Usage Notes ...................................................................................................................... 286
2
C Bus Interface (IIC) .....................................................................233
Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ..................................................................................... 231
I
Slave Address Register (SAR).......................................................................... 238
Second Slave Address Register (SARX) .......................................................... 238
I
I
I
Timer Serial Control Register (TSCR) ............................................................. 248
I
Master Transmit Operation ............................................................................... 251
Master Receive Operation................................................................................. 253
Slave Receive Operation................................................................................... 255
Slave Transmit Operation ................................................................................. 258
Clock Synchronous Serial Format .................................................................... 259
IRIC Setting Timing and SCL Control ............................................................. 260
Noise Canceler.................................................................................................. 261
Sample Flowcharts............................................................................................ 262
A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 278
A/D Control/Status Register (ADCSR) ............................................................ 279
A/D Control Register (ADCR) ......................................................................... 280
Single Mode...................................................................................................... 281
Scan Mode ........................................................................................................ 281
Input Sampling and A/D Conversion Time ...................................................... 282
External Trigger Input Timing.......................................................................... 283
2
2
2
2
2
C Bus Data Register (ICDR) .......................................................................... 236
C Bus Mode Register (ICMR)........................................................................ 239
C Bus Control Register (ICCR)...................................................................... 242
C Bus Status Register (ICSR)......................................................................... 245
C Bus Data Format ......................................................................................... 249
Rev. 6.00 Mar. 24, 2006 Page xv of xxviii
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