HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 301
![IC H8 MCU FLASH 32K 64QFP](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
HD64F3664H
Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664H
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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• Notes on WAIT Function
Conditions to cause this phenomenon
Error phenomenon
Restrictions
SDA
SCL
BC2 to BC0
IRIC
example)
(operation
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
Normally, WAIT state will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT state. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT state will be cancelled right after WAIT insertion on 8th clock fall.
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in the low state after the
counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure
15.18.)
and the fall of the 8th clock.
Figure 15.18 IRIC Flag Clear Timing on WAIT Operation
A
9
0
IRIC flag clear available
1
7
2
6
Transmit/receive data
3
5
4
4
5
3
IRIC flag clear unavailable
6
2
7
1
8
'L' confirm
SCL =
IRIC flag clear available
0
IRIC clear
A
Rev. 6.00 Mar. 24, 2006 Page 271 of 412
9
Transmit/receive
Section 15 I
1
7
data
2
6
When BC2 to BC0
clear IRIC
3
5
2
C Bus Interface (IIC)
REJ09B0142-0600
2
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