M30291FATHP Renesas Electronics America, M30291FATHP Datasheet - Page 266

• Manufacturer Part Number: M30291FATHP
• Description: IC M16C MCU FLASH 96K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30291FATHP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.1 Outline of Interrupt
Chapter 5
When an interrupt request is acknowledged, control branches to the interrupt routine that is set to an inter-
rupt vector table. Each interrupt vector table must have had the start address of its corresponding interrupt
routine set. For details about the interrupt vector table, refer to Section 1.10, “Vector Table.”
Figure 5.1.1. Classification of interrupts
Table 5.1.1 Interrupt Source (Nonmaskable) and Fixed Vector Table
*1 This interrupt is used exclusively for debugger purposes.
________
_______
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
5.1.1 Types of Interrupts
Figure 5.1.1 lists the types of interrupts. Table 5.1.1 lists the source of interrupts (nonmaskable) and the
fixed vector tables.
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Interrupt source
Interrupt
*1
Maskable interrupt:
Nonmaskable interrupt: This type of interrupt cannot be controlled by using the I flag to enable (or disable)
*1
Interrupt
Software
Hardware
Address (L) to address (H)
Vector table addresses
FFFDC
FFFEC
FFFE8
FFFFC
FFFE4
FFFF4
FFFF8
FFFE0
FFFF0
This type of interrupt can be controlled by using the I flag to enable (or
disable) an interrupt or by changing the interrupt priority level.
an interrupt or by changing the interrupt priority level.
16
16
16
16
16
16
16
16
16
to FFFEB
to FFFFB
to FFFF3
to FFFF7
to FFFE3
to FFFE7
to FFFEF
to FFFDF
to FFFFF
Special
Peripheral I/O
16
16
16
16
16
16
16
16
16
248
Interrupt generated by the UND instruction.
Interrupt generated by the INTO instruction.
Executed beginning from address indicated by vector in
variable vector table if all vector contents are FF
Can be controlled by an interrupt enable bit.
Normally do not use this interrupt.
Normally do not use this interrupt.
External interrupt generated by driving NMI pin low.
*1
_______
________
Undefined instruction (UND instruc-
tion)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
NMI
DBC
Watchdog timer
Single step
Address matched
Remarks
5.1 Outline of Interrupt
_______
16