MC68HC908AP8CB Freescale Semiconductor, MC68HC908AP8CB Datasheet - Page 215

• Manufacturer Part Number: MC68HC908AP8CB
• Description: IC MCU 8K FLASH 8MHZ 42SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AP8CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.5.2 Transmission Format When CPHA = 0
Figure 13-4
replacement for data sheet parametric information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured
as general-purpose I/O not affecting the SPI. (See
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
Freescale Semiconductor
13-5.
CAPTURE STROBE
shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
MASTER SS
SPSCK CYCLE #
MISO/MOSI
FROM MASTER
SS; TO SLAVE
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
FROM SLAVE
MOSI
MISO
Figure 13-4. Transmission Format (CPHA = 0)
MC68HC908AP Family Data Sheet, Rev. 4
MSB
BYTE 1
MSB
Figure 13-5. CPHA/SS Timing
1
BIT 6
BIT 6
2
BIT 5
BIT 5
3
13.7.2 Mode Fault
BYTE 2
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
Error.) When CPHA = 0, the first
6
BYTE 3
BIT 1
BIT 1
7
LSB
LSB
8
Transmission Formats
213