MC908SR12CFAE Freescale Semiconductor, MC908SR12CFAE Datasheet - Page 137
![IC MCU 12K FLASH 8MHZ 48-LQFP](/photos/12/45/124574/mc908sr12cfae_sml.jpg)
MC908SR12CFAE
Manufacturer Part Number
MC908SR12CFAE
Description
IC MCU 12K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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8.9 Acquisition/Lock Time Specifications
8.9.1 Acquisition/Lock Time Definitions
8.9.2 Parametric Influences on Reaction Time
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5 percent acquisition time tolerance.
If a command instructs the system to change from 0Hz to 1MHz, the
acquisition time is the time taken for the frequency to reach
1MHz ±50kHz. 50kHz = 5% of the 1MHz step input. If the system is
operating at 1MHz and suffers a –100kHz noise hit, the acquisition time
is the time taken to return from 900kHz to 1MHz ±5kHz. 5kHz = 5% of
the 100kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
Clock Generator Module (CGM)
Data Sheet
137
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