MC908SR12CFAE Freescale Semiconductor, MC908SR12CFAE Datasheet - Page 159
![IC MCU 12K FLASH 8MHZ 48-LQFP](/photos/12/45/124574/mc908sr12cfae_sml.jpg)
MC908SR12CFAE
Manufacturer Part Number
MC908SR12CFAE
Description
IC MCU 12K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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9.7 Low-Power Modes
9.7.1 Wait Mode
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described in
the following subsections. Both STOP and WAIT clear the interrupt mask
(I) in the condition code register, allowing interrupts to occur.
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode also can be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is logic 0, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
Figure 9-16
R/W
IDB
IAB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
System Integration Module (SIM)
last instruction.
WAIT ADDR
and
Figure 9-15. Wait Mode Entry Timing
Figure 9-15
PREVIOUS DATA
Figure 9-17
WAIT ADDR + 1
shows the timing for wait mode entry.
show the timing for WAIT recovery.
NEXT OPCODE
SAME
System Integration Module (SIM)
SAME
Low-Power Modes
SAME
SAME
Data Sheet
159
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