MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 35

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Freescale Semiconductor
$003A
$003B
$003C
$003D
$003E
$003F
$FE00
$FE01
$FE02
$FE03
$FE04
Addr.
1. Writing a 0 clears SBSW.
PLL Reference Divider Select
SIM Break Status Register
SIM Reset Status Register
Interrupt Status Register 1
ADC Status and Control
PLL VCO Select Range
SIM Break Flag Control
Register Name
ADC Clock Register
ADC Data Register
Register (ADSCR)
Register (SBFCR)
Register (PMRS)
Register (PMDS)
See page 220.
See page 172.
See page 220.
See page 167.
See page 69.
See page 70.
See page 51.
See page 53.
See page 53.
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
Reserved
Reserved
(ADCLK)
(SRSR)
(SBSR)
(INT1)
(ADR)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
COCO
ADIV2
VRS7
BCFE
Bit 7
POR
AD7
IF6
R
R
R
R
R
0
0
0
0
0
0
1
0
0
0
= Unimplemented
ADIV1
VRS6
AIEN
AD6
PIN
IF5
R
R
R
R
R
6
1
0
0
0
0
0
0
0
0
0
ADCO
ADIV0
VRS5
COP
AD5
IF4
R
R
R
R
R
5
0
0
0
0
0
0
0
0
0
0
R = Reserved
ADICLK
ADCH4
Unaffected by reset
VRS4
ILOP
AD4
IF3
R
R
R
R
R
4
0
0
0
1
0
0
0
0
0
0
ADCH3
VRS3
RDS3
ILAD
IF2
A3
R
R
R
R
R
3
0
0
1
0
0
0
0
0
0
0
U = Unaffected
MODRST
ADCH2
RDS2
VRS2
AD2
IF1
Input/Output (I/O) Section
R
R
R
R
R
2
0
0
1
0
0
0
0
0
0
0
(Note 1)
ADCH1
SBSW
RDS1
VRS1
AD1
LVI
R
R
R
R
1
0
0
1
0
0
0
0
0
0
0
0
ADCH0
VRS0
RDS0
Bit 0
AD0
R
R
R
R
R
0
1
1
0
0
0
0
0
0
0
0
0
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