MCHLC908QY2CPE Freescale Semiconductor, MCHLC908QY2CPE Datasheet - Page 109

• Manufacturer Part Number: MCHLC908QY2CPE
• Description: IC MCU 1.5K FLASH 8MHZ 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHLC908QY2CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see
free-running after all reset states. See
internal reset recovery sequences.
13.6 Exception Control
Normal sequential program execution can be changed in three different ways:
13.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 13-7
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first.
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
Freescale Semiconductor
1. Interrupts
2. Reset
3. Break interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
flow charts the handling of system interrupts.
Figure 13-10
Figure 13-9
demonstrates what happens when two interrupts are pending. If an interrupt
MC68HLC908QY/QT Family Data Sheet, Rev. 3
shows interrupt recovery timing.
13.4.2 Active Resets from Internal Sources
13.7.2 Stop Mode
for details.) The SIM counter is
for counter control and
Figure 13-8
Exception Control
shows
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