MCHLC908QY2CPE Freescale Semiconductor, MCHLC908QY2CPE Datasheet - Page 87

• Manufacturer Part Number: MCHLC908QY2CPE
• Description: IC MCU 1.5K FLASH 8MHZ 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHLC908QY2CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Polling and forced reset operation modes can be combined to take full advantage of LVD and LVR trip
voltages selection. LVD (LVDLVR = 1) in polling mode (LVIRSTD = 1) can be used as a low voltage
warning in a slowly and continuously falling V
has been identified, the part can be set to LVR (LVDLVR = 0) and reset enabled (LVIRSTD = 0). So, as
V
registers, LVIRSTD and LVDLVR bits are allowed to be written multiple times after reset.
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
LVI resets have been disabled
LVIOUT — LVI Output Bit
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
Freescale Semiconductor
DD
This read-only flag becomes set when the V
when V
that prevents oscillation into and out of reset (see
continues to fall the part will reset when LVR trip voltage is reached. Unlike other bits in CONFIG
DD
Address: $FE0C
voltage rises above V
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V
16.5 DC Electrical Characteristics
Reset:
Read:
Write:
LVIOUT
Bit 7
0
= Unimplemented
.
Figure 10-2. LVI Status Register (LVISR)
V
TRIPF
TRIPF
MC68HLC908QY/QT Family Data Sheet, Rev. 3
6
0
0
V
Table 10-1. LVIOUT Bit Indication
V
TRIPR
DD
DD
< V
[LVD] or V
V
> V
< V
DD
DD
. The difference in these threshold levels results in a hysteresis
TRIPR
TRIPF
5
0
0
< V
DD
TRIPR
DD
application (for example, battery applications). Once LVD
TRIPF
DD
NOTE
voltage falls below the V
for the actual trip point voltages.
4
0
0
voltage was detected below the V
Table
[LVR]) may be lower than this. See
Previous value
10-1). Reset clears the LVIOUT bit.
R
3
0
0
LVIOUT
0
1
= Reserved
2
0
0
TRIPF
1
0
0
trip voltage and is cleared
Bit 0
TRIPF
R
0
LVI Status Register
level while
87