MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 33
MC68HC711D3CFNE2
Manufacturer Part Number
MC68HC711D3CFNE2
Description
IC MCU 8BIT 3MHZ 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711D3CFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711D3CFNE2
Manufacturer:
ALLEGEO
Quantity:
4 492
Company:
Part Number:
MC68HC711D3CFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 3
Central Processor Unit (CPU)
3.1 Introduction
This section presents information on M68HC11 central processor unit (CPU):
The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as
addresses in the 64-Kbyte memory map. This is referred to as memory-mapped I/O. I/O has no
instructions separate from those used by memory. This architecture also allows accessing an operand
from an external memory location with no execution time penalty.
3.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory
locations. The seven registers, discussed in the following paragraphs, are shown in
Freescale Semiconductor
•
•
•
•
•
Architecture
Data types
Addressing modes
Instruction set
Special operations such as subroutine calls and interrupts
7
15
15
15
15
15
CONDITION CODE REGISTER
ACCUMULATOR A
DOUBLE ACCUMULATOR D
PROGRAM COUNTER
Figure 3-1. Programming Model
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
MC68HC711D3 Data Sheet, Rev. 2.1
0
7
7
S
X
ACCUMULATOR B
H
I
N
Z
V
C
0
0
0
0
0
0
0
A:B
D
IX
IY
SP
PC
CCR
CARRY
OVERFLOW
ZERO
NEGATIVE
I INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X INTERRUPT MASK
STOP DISABLE
Figure
3-1.
33