MC908QL4MDTE Freescale Semiconductor, MC908QL4MDTE Datasheet - Page 122

• Manufacturer Part Number: MC908QL4MDTE
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QL4MDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

System Integration Module (SIM)
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least
every 4080 BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible
out of reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break
auxiliary register (BRKAR).
13.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
13.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources. See
13.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the V
bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the
122
ADDRESS BUS
BUSCLKX4
BUSCLKX2
PORRST
OSC1
RST
CYCLES
4096
MC68HC908QL4 Data Sheet, Rev. 8
Figure 13-6. POR Recovery
(RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR)
CYCLES
32
DD
CYCLES
voltage falls to the LVI trip voltage V
32
Figure 2-1. Memory Map
$FFFE
Freescale Semiconductor
for memory ranges.
TRIPF
$FFFF
. The LVI