M30263F6AFP#U7 Renesas Electronics America, M30263F6AFP#U7 Datasheet - Page 93
![IC M16C/26A MCU FLASH 42SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U7
Manufacturer Part Number
M30263F6AFP#U7
Description
IC M16C/26A MCU FLASH 42SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U7
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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9.5 Interrupt Priority
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Figure 9.5.1. Hardware Interrupt Priority
6
0
9.4.4 Returning from an Interrupt Routine
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.5.1
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
9.5.1 Interrupt Priority Resolution Circuit
2
C
9
0 .
B
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 9.5.1.1 shows the circuit that judges the interrupt priority level.
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page 74
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Oscillation stop and re-oscillation
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voltage down detection
1
6
Peripheral function
Watchdog Timer,
C
Address match
2 /
Single step
detection,
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Reset
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DBC
NMI
High
Low
9. Interrupt
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