MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 180

• Manufacturer Part Number: MC9S12XA512VAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.4
The ATD is structured in an analog and a digital sub-block.
5.4.1
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V
5.4.1.1
The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them
as capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw
their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the
analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V
5.4.1.2
The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold
machine.
5.4.1.3
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly
charged to the sample potential.
5.4.1.4
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8
or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the
stored analog sample potential with a series of digitally generated analog potentials. By following a binary
search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled
potential.
When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent
current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power
consumption.
Only analog input signals within the potential range of V
in a non-railed digital output codes.
180
Functional Description
Analog Sub-Block
Sample and Hold Machine
Analog Input Multiplexer
Sample Buffer Amplifier
Analog-to-Digital (A/D) Machine
DDA
and V
SSA
allow to isolate noise of other MCU circuitry from the analog sub-block.
MC9S12XDP512 Data Sheet, Rev. 2.21
RL
to V
RH
(A/D reference potentials) will result
SSA
Freescale Semiconductor
to V
DDA
.