R5F21217JFP#U0 Renesas Electronics America, R5F21217JFP#U0 Datasheet - Page 447
R5F21217JFP#U0
Manufacturer Part Number
R5F21217JFP#U0
Description
IC R8C/20 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F21217JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21217JFP#U0R5F21217JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21217JFP#U0R5F21217JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
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R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
21.2
21.2.1
21.2.2
21.2.3
Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU
reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt
sequence. At this time, the acknowledged interrupt IR bit is set to 0.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause a problem that the interrupt is canceled, or an unexpected interrupt
is generated.
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting any value in the SP, the program may run out of control.
Either an “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal
input to the INT0 to INT3 pins and KI0 to KI3 pins regardless of the CPU clocks. For details, refer to Table
20.19 External Interrupt INTi (i = 0 to 3) Input, Table 20.25 External Interrupt INTi (i = 0 to 3) Input.
Notes on Interrupts
Reading Address 00000h
SP Setting
External Interrupt and Key Input Interrupt
Page 429 of 458
21. Usage Notes
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