R5F21217JFP#U0 Renesas Electronics America, R5F21217JFP#U0 Datasheet - Page 485

• Manufacturer Part Number: R5F21217JFP#U0
• Description: IC R8C/20 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
0.20
REVISION HISTORY
Jun 28, 2006
Date
343 to 385 17. Hardware LIN;
Page
300
301
304
306
309
338
339
340
341
342
345
346
16.2.5.4 Data Transmission/Reception;
16.2.5.4 Data Transmission/Reception, on the 5th line from the bottom;
Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock
Synchronous Communication Mode) revised.
16.2.6.2 Data Transmission;
16.2.6.2 Data Transmission, on the 9th line from the bottom;
16.2.6.3 Data Reception;
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select;
Figure 16.46 Example of Register Setting in Master Transmit Mode (I
Bus Interface Mode);
Figure 16.47 Example of Register Setting in Master Receive Mode (I
Bus Interface Mode);
Figure 16.48 Example of Register Setting in Slave Transmit Mode (I
Bus Interface Mode);
Figure 16.49 Example of Register Setting in Slave Receive Mode (I
Bus Interface Mode);
16.3.8 Notes on I
Figure 17.2 LINCR Register revised.
Figure 17.3 LINST Register revised.
R8C/20 Group, R8C/21 Group Hardware Manual
“16.2.5.4 Data Transmit/Receive” → “16.2.5.4 Data Transmission/
Reception” revised.
“When setting the ~ transmit is enabled.” deleted.
“16.2.6.2 Data Transmit” → “16.2.6.2 Data Transmission” revised.
“When setting the ~ transmit is enabled.” deleted.
“16.2.6.3 Data Receive” → “16.2.6.3 Data Reception” revised.
“16.2.8 Precautions on Clock Synchronous Serial I/O with Chip Select” →
“16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select” revised.
“Figure 16.46 Example of Register Setting in Master Transmit Mode
(Clock Synchronous Serial)” → “Figure 16.46 Example of Register
Setting in Master Transmit Mode (I
“Figure 16.47 Example of Register Setting in Master Receive Mode
(Clock Synchronous Serial)” → “Figure 16.47 Example of Register
Setting in Master Receive Mode (I
“Figure 16.48 Example of Register Setting in Slave Transmit Mode
(Clock Synchronous Serial)” → “Figure 16.48 Example of Register
Setting in Slave Transmit Mode (I
“Figure 16.49 Example of Register Setting in Slave Receive Mode
(Clock Synchronous Serial)” → “Figure 16.49 Example of Register
Setting in Slave Receive Mode (I
“16.3.8 Precautions on I
Interface” revised.
“Sync” → “Synch” revised.
2
C - 9
O Bus Interface;
2
O Bus Interface” → “16.3.8 Notes on I
Description
Summary
2
2
C Bus Interface Mode)” revised.
2
C Bus Interface Mode)” revised.
2
C Bus Interface Mode)” revised.
C Bus Interface Mode)” revised.
2
O Bus
2
2
C
2
C
2
C
C