MC9S08DV16MLF Freescale Semiconductor, MC9S08DV16MLF Datasheet - Page 160
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MC9S08DV16MLF
Manufacturer Part Number
MC9S08DV16MLF
Description
IC MCU 16K FLASH 1K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV16MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
MC9S08DV16MLF
Manufacturer:
Freescale Semiconductor
Quantity:
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
160
3. Then, BLPE mode transitions into PBE mode:
4. Last, PBE mode transitions into PEE mode:
c) MCGC1 = 0x98 (%10011000)
d) MCGC3 = 0x44 (%01000100)
e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS
a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode
b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
a) MCGC1 = 0x18 (%00011000)
b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected
– RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1
– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the
– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz.
clock is the PLL
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
to feed MCGOUT in the current clock mode
– Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16,
MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV
does not matter because both the FLL and PLL are disabled. Changing them only sets up the
the dividers for PLL usage in PBE mode
MCG for PLL usage in PBE mode
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
system clock source
MCGOUT = [(8 MHz / 8) * 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8
MHz
MC9S08DV60 Series Data Sheet, Rev 3
Freescale Semiconductor
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