MC9S08DZ60CLF Freescale Semiconductor, MC9S08DZ60CLF Datasheet - Page 112
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MC9S08DZ60CLF
Manufacturer Part Number
MC9S08DZ60CLF
Description
IC MCU 60K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ60CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ60CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 6 Parallel Input/Output Control
6.5.7.3
6.5.7.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
112
PTGPE[5:0]
PTGSE[5:0]
Reset:
Reset:
Field
Field
5:0
5:0
rate control to the desired value to ensure correct operation.
W
W
R
R
Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
Port G Pull Enable Register (PTGPE)
0
0
Port G Slew Rate Enable Register (PTGSE)
0
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 6-44. Internal Pull Enable for Port G Register (PTGPE)
Figure 6-45. Slew Rate Enable for Port G Register (PTGSE)
0
0
0
0
6
6
Table 6-42. PTGPE Register Field Descriptions
Table 6-43. PTGSE Register Field Descriptions
PTGPE5
PTGSE5
MC9S08DZ60 Series Data Sheet, Rev. 4
0
0
5
5
PTGPE4
PTGSE4
NOTE
0
0
4
4
Description
Description
PTGPE3
PTGSE3
3
0
3
0
PTGPE2
PTGSE2
0
0
2
2
PTGPE1
PTGSE1
Freescale Semiconductor
0
0
1
1
PTGPE0
PTGSE0
0
0
0
0
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