MC9S08DZ60CLF Freescale Semiconductor, MC9S08DZ60CLF Datasheet - Page 225
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MC9S08DZ60CLF
Manufacturer Part Number
MC9S08DZ60CLF
Description
IC MCU 60K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ60CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ60CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
INITRQ
The MSCAN must be in normal mode for this bit to become set.
See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
the CPU enters wait (CSWAI = 1) or stop mode (see
“Operation in Stop
The CPU has to make sure that the WUPE bit and the WUPIE wake-up interrupt enable bit (see
Receiver Interrupt Enable Register
The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
Not including WUPE, INITRQ, and SLPRQ.
TSTAT1 and TSTAT0 are not affected by initialization mode.
RSTAT1 and RSTAT0 are not affected by initialization mode.
SLPRQ
Field
1
0
6,7
5
Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving
mode (see
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see
cannot be set while the WUPIF flag is set (see
Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running — The MSCAN functions normally
1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see
Section 12.5.5.5, “MSCAN Initialization
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 12.3.2, “MSCAN Control Register 1
The following registers enter their hard reset state and restore their default values: CANCTL0
CANRIER
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
Mode”)
10
Section 12.5.5.4, “MSCAN Sleep
Table 12-1. CANCTL0 Register Field Descriptions (continued)
, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
.
(CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
MC9S08DZ60 Series Data Sheet, Rev. 4
Mode”). Any ongoing transmission or reception is aborted and
Section 12.5.5.2, “Operation in Wait
Section 12.3.2, “MSCAN Control Register 1
Mode”). The sleep mode request is serviced when the CAN bus is
(CANCTL1)”).
Section 12.3.4.1, “MSCAN Receiver Flag Register
Description
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Mode” and
Section 12.3.5, “MSCAN
(CANCTL1)”). SLPRQ
Section 12.5.5.3,
8
, CANRFLG
(CANRFLG)”).
9
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