AD8132ARZ Analog Devices Inc, AD8132ARZ Datasheet - Page 24

• Manufacturer Part Number: AD8132ARZ
• Description: IC AMP DIFF LDIST LP 70MA 8SOIC
• Manufacturer: Analog Devices Inc
• Type: Differential Ampr

Specifications of AD8132ARZ

• Amplifier Type: Differential
• Number Of Circuits: 1
• Output Type: Differential
• Slew Rate: 1200 V/µs
• -3db Bandwidth: 360MHz
• Current - Input Bias: 3µA
• Voltage - Input Offset: 1000µV
• Current - Supply: 12mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 11 V, ±1.35 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Channels: 1
• Number Of Elements: 1
• Power Supply Requirement: Single/Dual
• Common Mode Rejection Ratio: 70dB
• Voltage Gain Db: 0.129dB
• Input Resistance: 3@5VMohm
• Input Offset Voltage: 3.5@5VmV
• Input Bias Current: 7@5VnA
• Single Supply Voltage (typ): 3/5/9V
• Dual Supply Voltage (typ): ±3/±5V
• Power Supply Rejection Ratio: 70dB
• Power Dissipation: 250mW
• Rail/rail I/o Type: No
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 11V
• Dual Supply Voltage (min): ±1.35V
• Dual Supply Voltage (max): ±5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• No. Of Amplifiers: 1
• Gain Db Max: 1.015dB
• Bandwidth: 350MHz
• Supply Voltage Range: ± 1.35V To ± 5.5V
• Supply Current: 10.7mA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD8132
When using the AD8132 in gain configurations where β1 ≠ β2,
differential output noise appears due to input-referred voltage
noise in the V
where:
V
V
CALCULATING INPUT IMPEDANCE OF THE
APPLICATION CIRCUIT
The effective input impedance of a circuit, such as that in Figure 64,
at +D
driven by a single-ended or differential signal source. For balanced
differential input signals, the input impedance (R
the inputs (+D
In the case of a single-ended input signal (for example, if −D
is grounded and the input signal is applied to +D
impedance becomes
The circuit input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, R
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The AD8132 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this implies that the voltage
at −D
voltage (at V−) of the amplifier is also set to 0 V.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The V
approximately equal to the midsupply point (average value of the
voltage on V+ and V−). Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
OND
NOCM
R
V
is the output differential noise.
R
IN
IN
IN, dm
OCM
OND
is the input-referred voltage noise on V
IN,
and −D
in Figure 64 is 0 V when the negative power supply
dm
pin of the AD8132 is internally biased at a voltage
=
= 2 × R
=
2
⎛
⎜
⎜
⎜
⎜
⎝
OCM
V
IN
1
IN
NOCM
−
and −D
, depends on whether the amplifier is being
circuitry according to the following formula:
G
2
×
⎡
⎢
⎢
⎣
R
(
R
β1
β1
G
R
G
IN
F
+
−
+
) is simply
G
.
R
β2
β2
F
)
⎤
⎥
⎥
⎦
⎞
⎟
⎟
⎟
⎟
⎠
OCM
IN
.
IN, dm
), the input
) between
IN
Rev. I | Page 24 of 32
In cases where more accurate control of the output common-mode
level is required, it is a best practice that an external source or
resistor divider (with R
common-mode offset values in the Specifications section assume
the V
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the pin and bond wire
inductance of the AD8132, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance must be small to avoid destabilizing the amplifier. An
alternative technique is to place a small resistor in series with
the amplifier outputs, as shown in Figure 60.
OPEN-LOOP GAIN AND PHASE
Open-loop gain and phase plots are shown in Figure 65 and
Figure 66.
OCM
–100
–120
–140
–160
–180
–200
–10
–20
–20
–40
–60
–80
60
50
40
30
20
10
40
20
0
0
0.1
0.1
input is driven by a low impedance voltage source.
Figure 66. Open-Loop Phase vs. Frequency
Figure 65. Open-Loop Gain vs. Frequency
1
1
SOURCE
FREQUENCY (MHz)
FREQUENCY (MHz)
< 10 kΩ) be used. The output
10
10
R
R
100
100
L, dm
L, dm
= 2kΩ
= 2kΩ
1000
1000