AD8032ANZ Analog Devices Inc, AD8032ANZ Datasheet - Page 15

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AD8032ANZ

Manufacturer Part Number
AD8032ANZ
Description
IC OPAMP VF R-R DUAL LP 8DIP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8032ANZ

Slew Rate
35 V/µs
Amplifier Type
Voltage Feedback
Number Of Circuits
2
Output Type
Rail-to-Rail
-3db Bandwidth
80MHz
Current - Input Bias
450nA
Voltage - Input Offset
1000µV
Current - Supply
900µA
Current - Output / Channel
15mA
Voltage - Supply, Single/dual (±)
2.7 V ~ 12 V, ±1.35 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Op Amp Type
High Speed
No. Of Amplifiers
2
Bandwidth
80MHz
Supply Voltage Range
2.7V To 12V
Amplifier Case Style
DIP
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Gain Bandwidth Product
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
DRIVING CAPACITIVE LOADS
Capacitive loads interact with an op amp’s output impedance to
create an extra delay in the feedback path. This reduces circuit
stability and can cause unwanted ringing and oscillation. A
given value of capacitance causes much less ringing when the
amplifier is used with a higher noise gain.
The capacitive load drive of the AD8031/AD8032 can be
increased by adding a low valued resistor in series with the
capacitive load. Introducing a series resistor tends to isolate the
capacitive load from the feedback loop, thereby diminishing its
influence. Figure 46 shows the effects of a series resistor on the
capacitive drive for varying voltage gains. As the closed-loop
gain is increased, the larger phase margin allows for larger
capacitive loads with less overshoot. Adding a series resistor at
lower closed-loop gains accomplishes the same effect. For large
capacitive loads, the frequency response of the amplifier is
dominated by the roll-off of the series resistor and capacitive load.
Rev. D | Page 15 of 20
1000
100
10
1
Figure 46. Capacitive Load Drive vs. Closed-Loop Gain
0
V
200mV STEP
WITH 30% OVERSHOOT
R
S
S
= 5V
= 0Ω, 5Ω
R
1
S
= 20Ω
CLOSED-LOOP GAIN (V/V)
2
R
G
R
3
AD8031/AD8032
S
R
= 20Ω
F
R
R
S
4
S
= 5Ω
R
S
V
C
= 0Ω
OUT
L
5

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