AD826ARZ Analog Devices Inc, AD826ARZ Datasheet - Page 10

IC OPAMP VF 50MHZ DUAL LP 8SOIC

AD826ARZ

Manufacturer Part Number
AD826ARZ
Description
IC OPAMP VF 50MHZ DUAL LP 8SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD826ARZ

Slew Rate
350 V/µs
Amplifier Type
Voltage Feedback
Number Of Circuits
2
Gain Bandwidth Product
50MHz
-3db Bandwidth
50MHz
Current - Input Bias
3.3µA
Voltage - Input Offset
500µV
Current - Supply
6.6mA
Current - Output / Channel
50mA
Voltage - Supply, Single/dual (±)
5 V ~ 36 V, ±2.5 V ~ 18 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Op Amp Type
Voltage Feedback
No. Of Amplifiers
2
Bandwidth
50MHz
Supply Voltage Range
5V To 36V
Amplifier Case Style
SOIC
No. Of Pins
8
Rail/rail I/o Type
No
Number Of Elements
2
Unity Gain Bandwidth Product
29MHz
Common Mode Rejection Ratio
80dB
Input Offset Voltage
2@±15VmV
Input Bias Current
6.6uA
Single Supply Voltage (typ)
9/12/15/18/24/28V
Dual Supply Voltage (typ)
±5/±15V
Voltage Gain In Db
72.04dB
Power Supply Rejection Ratio
75dB
Power Supply Requirement
Single/Dual
Shut Down Feature
No
Single Supply Voltage (min)
5V
Single Supply Voltage (max)
36V
Dual Supply Voltage (min)
±2.5V
Dual Supply Voltage (max)
±18V
Technology
Bipolar
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
Lead Free Status / Rohs Status
Compliant

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AD826
THEORY OF OPERATION
The AD826 is a low cost, wide band, high performance dual
operational amplifier which can drive heavy capacitive and
resistive loads. It also achieves a constant slew rate, bandwidth
and settling time over its entire specified temperature range.
The AD826 (Figure 35) consists of a degenerated NPN
differential pair driving matched PNPs in a folded-cascode gain
stage. The output buffer stage employs emitter followers in a
class AB amplifier which delivers the necessary current to the
load while maintaining low levels of distortion.
The capacitor, C
capacitive loads. With low capacitive loads, the gain from the
compensation node to the output is very close to unity. In this
case, C
compensation capacitance of the device. As the capacitive load
is increased, a pole is formed with the output impedance of the
output stage. This reduces the gain, and therefore, C
incompletely bootstrapped. Effectively, some fraction of C
contributes to the overall compensation capacitance, reducing
the unity gain bandwidth. As the load capacitance is further
increased, the bandwidth continues to fall, maintaining the
stability of the amplifier.
INPUT CONSIDERATIONS
An input protection resistor (R
circuits where the input to the AD826 will be subjected to
transient or continuous overload voltages exceeding the ±6 V
maximum differential limit. This resistor provides protection
for the input transistors by limiting their maximum base current.
–IN
+IN
F
is bootstrapped and does not contribute to the overall
NULL1
F
, in the output stage mitigates the effect of
Figure 35. Simplified Schematic
NULL8
IN
in Figure 25) is required in
C
F
F
is
+V
OUTPUT
–V
S
S
F
-10-
For high performance circuits, it is recommended that a
“balancing” resistor be used to reduce the offset errors caused
by bias current flowing through the input and feedback resistors.
The balancing resistor equals the parallel combination of R
and R
terminal. The offset voltage error will then be reduced by more
than an order of magnitude.
APPLYING THE AD826
The AD826 is a breakthrough dual amp that delivers precision
and speed at low cost with low power consumption. The AD826
offers excellent static and dynamic matching characteristics,
combined with the ability to drive heavy resistive and capacitive
loads. As with all high frequency circuits, care should be taken
to maintain overall device performance as well as their matching.
The following items are presented as general design considerations.
Circuit Board Layout
Input and output runs should be laid out so as to physically
isolate them from remaining runs. In addition, the feedback
resistor of each amplifier should be placed away from the
feedback resistor of the other amplifier, since this greatly
reduces inter-amp coupling.
Choosing Feedback and Gain Resistors
In order to prevent the stray capacitance present at each
amplifier’s summing junction from limiting its performance,
the feedback resistors should be ≤1 kΩ. Since the summing
junction capacitance may cause peaking, a small capacitor
(1 pF–5pF) maybe paralleled with R
Finally, sockets should be avoided, because of their tendency to
increase interlead capacitance.
Power Supply Considerations
To ensure the proper operation of the AD826, connect the
positive supply before the negative supply. Also, proper power
supply decoupling is critical to preserve the integrity of high
frequency signals. In carefully laid out designs, decoupling
capacitors should be placed in close proximity to the supply
pins, while their lead lengths should be kept to a minimum.
These measures greatly reduce undesired inductive effects on
the amplifier’s response.
Though two 0.1 μF capacitors will typically be effective in
decoupling the supplies, several capacitors of different values
can be paralleled to cover a wider frequency range.
F
and thus provides a matched impedance at each input
F
to neutralize this effect.
Rev. C
IN

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