PA04 Cirrus Logic Inc, PA04 Datasheet - Page 4

• Manufacturer Part Number: PA04
• Description: IC PWR AMP 200V 20A 12DIP
• Manufacturer: Cirrus Logic Inc
• Series: Apex Precision Power™r

Specifications of PA04

• Amplifier Type: Power
• Number Of Circuits: 1
• Slew Rate: 50 V/µs
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 10pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 70mA
• Current - Output / Channel: 20A
• Voltage - Supply, Single/dual (±): 30 V ~ 200 V, ±15 V ~ 100 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 12-DIP Module
• Number Of Channels: 1
• Voltage Gain Db: 102 dB
• Common Mode Rejection Ratio (min): 86 dB
• Input Offset Voltage: 10 mV
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Maximum Dual Supply Voltage: +/- 100 V
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1420; PA04

PA04 • PA04A
GENERAL
siderations" which covers stability, supplies, heat sinking,
mounting, current limit, SOA interpretation, and specification
interpretation. Visit www.cirrus.com for design tools that help
automate tasks such as calculations for stability, internal power
dissipation, current limit; heat sink selection; Apex Precision
Power’s complete Application Notes library; Technical Seminar
Workbook; and Evaluation Kits.
CURRENT LIMIT
across the current limit sense resistor. For the current limit to
work correctly pin 11 must be connected to the amplifier output
side and pin 10 connected to the load side of the current limit
resistor, R
any parasitic resistances, Rp, formed by sockets and solder
joints as well as internal amplifier losses. The current limiting
resistor may not be placed anywhere in the output circuit except
where shown in Figure 1.
follows:
Figure 1.
Current Limit.
SAFE OPERATING AREA (SOA)
fier has two distinct limitations:
1. The current handling capability of the MOSFET geometry
2. The junction temperature of the output MOSFETs.
NOTE: The output stage is protected against transient fly-
4
Please read Application Note 1 "General Operating Con-
The two current limit sense lines are to be connected directly
The value of the current limit resistor can be calculated as
The MOSFET output stage of this power operational ampli-
and the wire bonds.
back. However, for protection against sustained, high
energy flyback, external fast-recovery diodes should
be used.
CL
5.0
2.0
1.0
20
10
.5
.2
, as shown in Figure 1. This connection will bypass
2
SUPPLY TO OUTPUT DIFFERENTIAL (V)
5
10
INPUT
SOA
R i
20
R
CL
=
1
2
50
I
PA04
10
.76
LIMIT
CL
11
CL
100
7
200
R
f
R
P
R
CL
R
L
P r o d u c t I n n o v a t i o n F r o m
SLEEP MODE OPERATION
This disables the amplifier’s internal reference and the am-
plifier shuts down except for a trickle current of 3 mA which
flows into pin 12. Pin 12 should be left open if the sleep mode
is not required.
this mode. In Figure 2A a small signal relay is driven by a logic
gate. This removes the requirement to deal with the common
mode voltage that exists on the shutoff circuitry since the sleep
mode is referenced to the +V
mode input signal. The differential input activates sleep mode
with a differential logic level signal and allows common mode
voltages to ±V
BOOST OPERATION
amplifier are operated at higher supply voltages than the
amplifier’s high current output stage. +V
–V
the amplifier. +V
high current output stage. An additional 5V on the V
is sufficient to allow the small signal stages to drive the output
transistors into saturation and improve the output voltage
swing for extra efficient operation when required. When close
swings to the supply rails is not required the +V
pins must be strapped together as well as the –V
pins. The boost voltage pins must not be at a voltage lower
than the V
COMPENSATION
nected to pins 3 and 4. Unity gain stability can be achieved
at any compensation capacitance greater than 330 pF with at
least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate. Use the typical operating curves as
a guide to select C
FIGURE 2A. SLEEP MODE CIRCUIT.
FIGURE 2B. SLEEP MODE CIRCUIT.
In the sleep mode, pin 12 (sleep) is tied to pin 9 (+V
Several possible circuits can be built to take advantage of
In Figure 2B, circuitry is used to level translate the sleep
With the V
The external compensation components C
BOOST
LOGIC
(pin 5) are connected to the small signal circuitry of
+
-
S
LOGIC
INPUT
pins.
BOOST
470Ω
BOOST
470Ω
S
(pin 8) and –V
.
C
feature the small signal stages of the
Q1
Q2
and R
1KΩ
–V
K1
BOOST
560Ω
C
for the application.
BOOST
S
(pin 6) are connected to the
voltage.
12
12
9
9
BOOST
C
+V
+V
SLEEP
SLEEP
and R
BOOST
BOOST
BOOST
BOOST
(pin 9) and
BOOST
C
and +V
and –V
are con-
PA04U
BOOST
pins
).
S
S