LT1637HS8#TR Linear Technology, LT1637HS8#TR Datasheet - Page 12
![IC OPAMP R-R IN/OUT 1.1MHZ 8SOIC](/photos/12/47/124722/lt1637hs8_pbf_sml.jpg)
LT1637HS8#TR
Manufacturer Part Number
LT1637HS8#TR
Description
IC OPAMP R-R IN/OUT 1.1MHZ 8SOIC
Manufacturer
Linear Technology
Series
Over-The-Top®r
Datasheet
1.LT1637CS8PBF.pdf
(16 pages)
Specifications of LT1637HS8#TR
Amplifier Type
General Purpose
Number Of Circuits
1
Output Type
Rail-to-Rail
Slew Rate
0.4 V/µs
Gain Bandwidth Product
1.1MHz
Current - Input Bias
17nA
Voltage - Input Offset
100µV
Current - Supply
230µA
Current - Output / Channel
31.7mA
Voltage - Supply, Single/dual (±)
2.7 V ~ 44 V, ±1.35 V ~ 22 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
-3db Bandwidth
-
Other names
LT1637HS8TR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LT1637
APPLICATIO S I FOR ATIO
Gain
The open-loop gain is less sensitive to load resistance
when the output is sourcing current. This optimizes per-
formance in single supply applications where the load is
returned to ground. The typical performance photo of
Open-Loop Gain for various loads shows the details.
Shutdown
The LT1637 can be shut down two ways: using the
shutdown pin or bringing V
is brought to within 0.5V of V
output leakage current drop to less than 10nA. When the
shutdown pin is brought 1.2V above V
current drops to about 3µA and the output leakage current
is less than 1µA, independent of V
bias current is less than 0.1nA (even if the inputs are 44V
above the negative supply).
SI PLIFIED
12
W
SHDN
5
Q3
R1
1M
Q4
Q5
10µA
U
SCHE ATIC
Q6
R2
6k
Q7
Q1
Q2
U
+
W
– IN
+ IN
to within 0.5V of V
–
both the supply current and
2
3
Q8
+
. In either case the input
1.3k
1.3k
R3
R4
W
D4
–
, the supply
Q11
–
D5
. When V
U
Q9
D1
Q10
Q12
+
D2
The shutdown pin can be taken up to 32V above V
shutdown pin can be driven below V
current through the substrate diode should be limited with
an external resistor to less than 10mA.
Input Offset Nulling
The input offset voltage can be nulled by placing a 10k
potentiometer between Pins 1 and 8 with its wiper to V
(see Figure 1). The null range will be at least ±3mV.
Q14
NULL
Q15
Q13
1
Q16
R5
7k
R7
400Ω
Figure 1. Input Offset Nulling
Q17
R6
7k
R8
400Ω
Q18
8
D3
LT1637
NULL
1
10k
V
–
Q19
Q20
8
Q21
Q22
1637 F01
–
Q23
, however the pin
Q24
1637 SS
Q26
Q25
7 V
6 OUT
4 V
–
. The
+
–
1637fd
–