AD8017AR-REEL Analog Devices Inc, AD8017AR-REEL Datasheet - Page 11
![IC AMP GP DUAL LP LDIST 8SOIC](/photos/5/66/56684/505-8-soic_sml.jpg)
AD8017AR-REEL
Manufacturer Part Number
AD8017AR-REEL
Description
IC AMP GP DUAL LP LDIST 8SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD8017AR-EVAL.pdf
(16 pages)
Specifications of AD8017AR-REEL
Rohs Status
RoHS non-compliant
Amplifier Type
General Purpose
Number Of Circuits
2
Slew Rate
1600 V/µs
-3db Bandwidth
160MHz
Current - Input Bias
16µA
Voltage - Input Offset
1800µV
Current - Supply
7mA
Current - Output / Channel
270mA
Voltage - Supply, Single/dual (±)
4.4 V ~ 12 V, ±2.2 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Power Supply Requirement
Single/Dual
Package Type
SOIC N
Pin Count
8
For Use With
AD8017AR-EVAL - BOARD EVAL FOR AD8017
Output Type
-
Gain Bandwidth Product
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
THEORY OF OPERATION
The AD8017 is a dual high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion and signal swing,
under heavy current loads. Its wide dynamic performance
(including noise) is the result of both a new complementary
high speed bipolar process and a new and unique architectural
design. The AD8017 basically uses a two gain stage comple-
mentary design approach versus the traditional “single stage”
complementary mirror structure sometimes referred to as the
Nelson amplifier. Though twin stages have been tried before,
they typically consumed high power since they were of a folded
cascode design much like the AD9617.
This design allows for the standing or quiescent current to add
to the high signal or slew current-induced stages. In the time
domain, the large signal output rise/fall time and slew rate is
typically controlled by the small signal BW of the amplifier and
the input signal step amplitude respectively, not the dc quies-
cent current of the gain stages (with the exception of input level
shift diodes Q1/Q2). Using two stages as opposed to one, also
allows for a higher overall gain bandwidth product (GBWP) for
the same power, thus providing lower signal distortion and the
ability to drive heavier external loads. In addition, the second
gain stage also isolates (divides down) A3’s input reflected load
drive and the nonlinearities created resulting in relatively lower
distortion and higher open-loop gain. See Figure 6.
INP
IPP
+
V
P
–
Q1
Q2
V
N
Q3
Q4
IQ1
IQ1
IPN
IPN
A1
IE
A1
Z1
IR + IFC
IR – IFC
–V
–V
I
I
Z1 = R1 || C1
Z1
C
C
P
P
Z1
1
1
Overall, when “high” external load drive and low ac distortion is
a requirement, a twin gain stage integrating amplifier like the
AD8017 will provide excellent results for low power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus external
gain variations (varying R
VF op amp, where the BW varies inversely with gain. Another
key attribute of this amplifier is its ability to run on a single 5 V
supply due in part to its wide common-mode input and output
voltage range capability. For 5 V supply operation, the device
obviously consumes less than half the quiescent power (versus
12 V supply) with little degradation in its ac and dc performance
characteristics. See specification pages for comparisons.
DC GAIN CHARACTER
Gain stages A1/A1 and A2/A2 combined provide negative feed-
forward transresistance gain. See Figure 6. Stage A3 is a unity
gain buffer which provides external load isolation to A2. Each
stage uses a symmetrical complementary design. (A3 is also
complementary, though not explicitly shown). This is done to
reduce both second order signal distortion and overall quiescent
power as discussed above. In the quasi dc-to-low frequency
region, the closed loop gain relationship can be approximated as:
G = 1+R
G = –R
These basic relationships above are common to all traditional
operational amplifiers.
C
–A2
–A2
P
C
2
C
D
D
Z2
F
/R
F
/R
G
ICQ + IO
ICQ – IO
G
V
for Inverting Operation
O
for Noninverting Operation
9
–A3
AD8017
R
N
R
F
G
) will be much lower compared to a
R
L
C
L
V
O
AD8017