AD8556ARZ Analog Devices Inc, AD8556ARZ Datasheet - Page 18

• Manufacturer Part Number: AD8556ARZ
• Description: IC AMP CHOPPER 2MHZ 10MA 8SOIC
• Manufacturer: Analog Devices Inc
• Series: DigiTrim®r
• Type: Instrumentation Amplifierr

Specifications of AD8556ARZ

• Operating Temperature: -40°C ~ 140°C
• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Slew Rate: 1.2 V/µs
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 49nA
• Voltage - Input Offset: 2µV
• Current - Supply: 2mA
• Current - Output / Channel: 10mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 700kHz
• Rail To Rail I/o Type: Rail-Rail I/O
• No. Of Channels: 1
• Supply Voltage Range: 2.7V To 5.5V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Number Of Channels: 1
• Number Of Elements: 5
• Power Supply Requirement: Single
• Common Mode Rejection Ratio: 80dB
• Unity Gain Bandwidth Product (typ): 8MHz
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Rejection Ratio: 109dB
• Rail/rail I/o Type: Rail to Rail Input/Output
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 140C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Compliant

AD8556
OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a com-
parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or
(VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The inputs
to A1 and A2, VNEG and VPOS, are also pulled up to VDD by
currents IP1 and IP2. These are both nominally 49 nA and
matched to within 3 nA. If the inputs to A1 or A2 are accidentally
left floating, as with an open wire fault, IP1 and IP2 pull them
to VDD, which would cause VOUT to swing to VSS, allowing
this fault to be detected. It is not possible to disable IP1 and IP2,
nor the clamping of VOUT to VSS, when VNEG or VPOS
approaches VDD.
SHORTED WIRE FAULT DETECTION
The AD8556 provides fault detection when VPOS, VNEG, or
VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage
regions at VPOS, VNEG, and VCLAMP that trigger an error
condition. When an error condition occurs, the VOUT pin is
shorted to VSS. Table 7 lists the voltage levels shown in Figure 48.
Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage
VINH
VINL
VCLL
NORMAL
ERROR
ERROR
VPOS
Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP
Min (V)
2.95
1.95
1.05
VDD
VINH
VINL
VSS
that Trigger a Fault Condition
Typ (V)
3.0
2.0
1.1
NORMAL
ERROR
ERROR
VNEG
Max (V)
3.05
2.05
1.15
VDD
VINH
VINL
VSS
VOUT Condition
Short to VSS fault
detection
Short to VSS fault
detection
Short to VSS fault
detection
NORMAL
VCLAMP
ERROR
VDD
VCLL
VSS
Rev. A | Page 18 of 28
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the Shorted Wire Fault
Detection section. In this way, the VOUT pin is shorted to VSS
when a floating input is detected. Table 8 lists the currents used.
Table 8. Floating Fault Detection at VPOS, VNEG, and
VCLAMP
Mnemonic
VPOS
VNEG
VCLAMP
DEVICE PROGRAMMING
Digital Interface
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input pin,
DIGIN, has hysteresis to minimize the possibility of inadvertent
triggering with slow signals. It also has a pull-down current sink
to allow it to be left floating when programming is not being
performed. The pull-down ensures inactive status of the digital
input by forcing a dc low voltage on DIGIN.
A short pulse at DIGIN from low to high and back to low again,
such as between 50 ns and 10 μs long, loads 0 into the shift register.
A long pulse at DIGIN, such as 50 μs or longer, loads 1 into the
shift register. The time between pulses should be at least 10 μs.
Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 ×
VDD are recognized as a low, and voltages at DIGIN between
0.8 × VDD and VDD are recognized as a high. The timing
diagram example in Figure 49 shows the waveform for entering
code 010011 into the shift register.
Typical Current
49 nA pull-up
49 nA pull-up
0.2 μA pull-down
Goal of Current
Pull VPOS above VINH
Pull VNEG above VINH
Pull VCLAMP below VCLL